Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7447368 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
285376 |
| auto[1] |
5350067 |
1 |
|
|
T33 |
273527 |
|
T19 |
51 |
|
T1 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10610689 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
455528 |
| auto[1] |
2186746 |
1 |
|
|
T33 |
103375 |
|
T19 |
13 |
|
T1 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7481192 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
277800 |
| auto[1] |
5316243 |
1 |
|
|
T33 |
281103 |
|
T19 |
31 |
|
T1 |
13 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1554781 |
1 |
|
|
T33 |
89982 |
|
T19 |
2 |
|
T1 |
2 |
| auto[1] |
auto[0] |
auto[1] |
1087550 |
1 |
|
|
T33 |
51788 |
|
T19 |
8 |
|
T1 |
11 |
| auto[1] |
auto[1] |
auto[0] |
1574716 |
1 |
|
|
T33 |
87746 |
|
T19 |
16 |
|
T12 |
3108 |
| auto[1] |
auto[1] |
auto[1] |
1099196 |
1 |
|
|
T33 |
51587 |
|
T19 |
5 |
|
T12 |
4458 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |