Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7484376 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
280785 |
auto[1] |
5313059 |
1 |
|
|
T33 |
278118 |
|
T19 |
28 |
|
T1 |
39 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10609227 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
453809 |
auto[1] |
2188208 |
1 |
|
|
T33 |
105094 |
|
T19 |
25 |
|
T1 |
10 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7474398 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
275780 |
auto[1] |
5323037 |
1 |
|
|
T33 |
283123 |
|
T19 |
38 |
|
T1 |
23 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1581714 |
1 |
|
|
T33 |
88872 |
|
T19 |
10 |
|
T1 |
7 |
auto[1] |
auto[0] |
auto[1] |
1103689 |
1 |
|
|
T33 |
52310 |
|
T19 |
18 |
|
T12 |
4725 |
auto[1] |
auto[1] |
auto[0] |
1553115 |
1 |
|
|
T33 |
89157 |
|
T19 |
3 |
|
T1 |
6 |
auto[1] |
auto[1] |
auto[1] |
1084519 |
1 |
|
|
T33 |
52784 |
|
T19 |
7 |
|
T1 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |