Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7441896 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
288588 |
| auto[1] |
5355539 |
1 |
|
|
T33 |
270315 |
|
T19 |
7 |
|
T1 |
21 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10612355 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
454460 |
| auto[1] |
2185080 |
1 |
|
|
T33 |
104443 |
|
T19 |
7 |
|
T1 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7476556 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
279286 |
| auto[1] |
5320879 |
1 |
|
|
T33 |
279617 |
|
T19 |
38 |
|
T1 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1563530 |
1 |
|
|
T33 |
91149 |
|
T19 |
31 |
|
T1 |
1 |
| auto[1] |
auto[0] |
auto[1] |
1092274 |
1 |
|
|
T33 |
54159 |
|
T19 |
7 |
|
T1 |
8 |
| auto[1] |
auto[1] |
auto[0] |
1572269 |
1 |
|
|
T33 |
84025 |
|
T1 |
6 |
|
T12 |
2840 |
| auto[1] |
auto[1] |
auto[1] |
1092806 |
1 |
|
|
T33 |
50284 |
|
T12 |
4357 |
|
T14 |
74 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |