Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7450752 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
284776 |
| auto[1] |
5346683 |
1 |
|
|
T33 |
274127 |
|
T19 |
19 |
|
T1 |
53 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12125175 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
523596 |
| auto[1] |
672260 |
1 |
|
|
T33 |
35307 |
|
T1 |
1 |
|
T12 |
1982 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7482622 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
283391 |
| auto[1] |
5314813 |
1 |
|
|
T33 |
275512 |
|
T19 |
38 |
|
T1 |
34 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2314654 |
1 |
|
|
T33 |
120837 |
|
T19 |
37 |
|
T1 |
9 |
| auto[1] |
auto[0] |
auto[1] |
336454 |
1 |
|
|
T33 |
18051 |
|
T12 |
1061 |
|
T14 |
21 |
| auto[1] |
auto[1] |
auto[0] |
2327899 |
1 |
|
|
T33 |
119368 |
|
T19 |
1 |
|
T1 |
24 |
| auto[1] |
auto[1] |
auto[1] |
335806 |
1 |
|
|
T33 |
17256 |
|
T1 |
1 |
|
T12 |
921 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |