Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7469246 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
277443 |
| auto[1] |
5328189 |
1 |
|
|
T33 |
281460 |
|
T19 |
27 |
|
T1 |
30 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10613119 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
455585 |
| auto[1] |
2184316 |
1 |
|
|
T33 |
103318 |
|
T19 |
14 |
|
T1 |
28 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7476725 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
281545 |
| auto[1] |
5320710 |
1 |
|
|
T33 |
277358 |
|
T19 |
35 |
|
T1 |
34 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1572737 |
1 |
|
|
T33 |
84720 |
|
T19 |
15 |
|
T1 |
3 |
| auto[1] |
auto[0] |
auto[1] |
1096836 |
1 |
|
|
T33 |
50535 |
|
T19 |
10 |
|
T1 |
25 |
| auto[1] |
auto[1] |
auto[0] |
1563657 |
1 |
|
|
T33 |
89320 |
|
T19 |
6 |
|
T1 |
3 |
| auto[1] |
auto[1] |
auto[1] |
1087480 |
1 |
|
|
T33 |
52783 |
|
T19 |
4 |
|
T1 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |