Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7460669 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
281362 |
| auto[1] |
5336766 |
1 |
|
|
T33 |
277541 |
|
T19 |
43 |
|
T1 |
27 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10601933 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
452554 |
| auto[1] |
2195502 |
1 |
|
|
T33 |
106349 |
|
T19 |
16 |
|
T1 |
13 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7439352 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
273329 |
| auto[1] |
5358083 |
1 |
|
|
T33 |
285574 |
|
T19 |
35 |
|
T1 |
29 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1584785 |
1 |
|
|
T33 |
88449 |
|
T19 |
14 |
|
T1 |
8 |
| auto[1] |
auto[0] |
auto[1] |
1099335 |
1 |
|
|
T33 |
52651 |
|
T19 |
9 |
|
T1 |
5 |
| auto[1] |
auto[1] |
auto[0] |
1577796 |
1 |
|
|
T33 |
90776 |
|
T19 |
5 |
|
T1 |
8 |
| auto[1] |
auto[1] |
auto[1] |
1096167 |
1 |
|
|
T33 |
53698 |
|
T19 |
7 |
|
T1 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |