Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7474042 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
287070 |
| auto[1] |
5323393 |
1 |
|
|
T33 |
271833 |
|
T19 |
27 |
|
T1 |
33 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10609983 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
457151 |
| auto[1] |
2187452 |
1 |
|
|
T33 |
101752 |
|
T19 |
8 |
|
T1 |
16 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7455611 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
288843 |
| auto[1] |
5341824 |
1 |
|
|
T33 |
270060 |
|
T19 |
24 |
|
T1 |
25 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1578095 |
1 |
|
|
T33 |
84757 |
|
T19 |
12 |
|
T1 |
7 |
| auto[1] |
auto[0] |
auto[1] |
1090634 |
1 |
|
|
T33 |
50440 |
|
T19 |
4 |
|
T1 |
2 |
| auto[1] |
auto[1] |
auto[0] |
1576277 |
1 |
|
|
T33 |
83551 |
|
T19 |
4 |
|
T1 |
2 |
| auto[1] |
auto[1] |
auto[1] |
1096818 |
1 |
|
|
T33 |
51312 |
|
T19 |
4 |
|
T1 |
14 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |