Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7458447 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
283710 |
| auto[1] |
5338988 |
1 |
|
|
T33 |
275193 |
|
T19 |
49 |
|
T1 |
28 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12126612 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
523496 |
| auto[1] |
670823 |
1 |
|
|
T33 |
35407 |
|
T19 |
1 |
|
T12 |
1796 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7492535 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
283400 |
| auto[1] |
5304900 |
1 |
|
|
T33 |
275503 |
|
T19 |
60 |
|
T1 |
31 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2315724 |
1 |
|
|
T33 |
124309 |
|
T19 |
27 |
|
T1 |
27 |
| auto[1] |
auto[0] |
auto[1] |
335235 |
1 |
|
|
T33 |
18484 |
|
T12 |
961 |
|
T14 |
19 |
| auto[1] |
auto[1] |
auto[0] |
2318353 |
1 |
|
|
T33 |
115787 |
|
T19 |
32 |
|
T1 |
4 |
| auto[1] |
auto[1] |
auto[1] |
335588 |
1 |
|
|
T33 |
16923 |
|
T19 |
1 |
|
T12 |
835 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |