Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7453340 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
281104 |
| auto[1] |
5344095 |
1 |
|
|
T33 |
277799 |
|
T19 |
42 |
|
T1 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12125399 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
523284 |
| auto[1] |
672036 |
1 |
|
|
T33 |
35619 |
|
T19 |
2 |
|
T12 |
1910 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7474860 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
278775 |
| auto[1] |
5322575 |
1 |
|
|
T33 |
280128 |
|
T19 |
61 |
|
T1 |
25 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2321858 |
1 |
|
|
T33 |
122944 |
|
T19 |
49 |
|
T1 |
25 |
| auto[1] |
auto[0] |
auto[1] |
335155 |
1 |
|
|
T33 |
18143 |
|
T19 |
2 |
|
T12 |
954 |
| auto[1] |
auto[1] |
auto[0] |
2328681 |
1 |
|
|
T33 |
121565 |
|
T19 |
10 |
|
T12 |
6724 |
| auto[1] |
auto[1] |
auto[1] |
336881 |
1 |
|
|
T33 |
17476 |
|
T12 |
956 |
|
T14 |
33 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |