Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7451531 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
273419 |
| auto[1] |
5345904 |
1 |
|
|
T33 |
285484 |
|
T19 |
34 |
|
T1 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12128019 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
524176 |
| auto[1] |
669416 |
1 |
|
|
T33 |
34727 |
|
T19 |
2 |
|
T1 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7492980 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
283823 |
| auto[1] |
5304455 |
1 |
|
|
T33 |
275080 |
|
T19 |
47 |
|
T1 |
29 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2313693 |
1 |
|
|
T33 |
118191 |
|
T19 |
30 |
|
T1 |
27 |
| auto[1] |
auto[0] |
auto[1] |
333614 |
1 |
|
|
T33 |
17053 |
|
T19 |
2 |
|
T1 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2321346 |
1 |
|
|
T33 |
122162 |
|
T19 |
15 |
|
T12 |
7027 |
| auto[1] |
auto[1] |
auto[1] |
335802 |
1 |
|
|
T33 |
17674 |
|
T12 |
1049 |
|
T14 |
25 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |