Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7500630 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
278630 |
| auto[1] |
5296805 |
1 |
|
|
T33 |
280273 |
|
T19 |
38 |
|
T1 |
25 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12125087 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
522735 |
| auto[1] |
672348 |
1 |
|
|
T33 |
36168 |
|
T19 |
3 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7475637 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
275037 |
| auto[1] |
5321798 |
1 |
|
|
T33 |
283866 |
|
T19 |
55 |
|
T1 |
39 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2338336 |
1 |
|
|
T33 |
122058 |
|
T19 |
41 |
|
T1 |
22 |
| auto[1] |
auto[0] |
auto[1] |
338096 |
1 |
|
|
T33 |
17777 |
|
T19 |
1 |
|
T12 |
955 |
| auto[1] |
auto[1] |
auto[0] |
2311114 |
1 |
|
|
T33 |
125640 |
|
T19 |
11 |
|
T1 |
16 |
| auto[1] |
auto[1] |
auto[1] |
334252 |
1 |
|
|
T33 |
18391 |
|
T19 |
2 |
|
T1 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |