Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7451042 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
277614 |
| auto[1] |
5346393 |
1 |
|
|
T33 |
281289 |
|
T19 |
14 |
|
T1 |
47 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12124268 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
524623 |
| auto[1] |
673167 |
1 |
|
|
T33 |
34280 |
|
T12 |
1988 |
|
T14 |
43 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7473903 |
1 |
|
|
T31 |
324 |
|
T32 |
15907 |
|
T33 |
288518 |
| auto[1] |
5323532 |
1 |
|
|
T33 |
270385 |
|
T19 |
35 |
|
T1 |
32 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2326228 |
1 |
|
|
T33 |
114951 |
|
T19 |
27 |
|
T1 |
16 |
| auto[1] |
auto[0] |
auto[1] |
336551 |
1 |
|
|
T33 |
16603 |
|
T12 |
895 |
|
T14 |
18 |
| auto[1] |
auto[1] |
auto[0] |
2324137 |
1 |
|
|
T33 |
121154 |
|
T19 |
8 |
|
T1 |
16 |
| auto[1] |
auto[1] |
auto[1] |
336616 |
1 |
|
|
T33 |
17677 |
|
T12 |
1093 |
|
T14 |
25 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |