Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4835114	1			T23	1		T24	185		T25	1
all_pins[1]	4835114	1			T23	1		T24	185		T25	1
all_pins[2]	4835114	1			T23	1		T24	185		T25	1
all_pins[3]	4835114	1			T23	1		T24	185		T25	1
all_pins[4]	4835114	1			T23	1		T24	185		T25	1
all_pins[5]	4835114	1			T23	1		T24	185		T25	1
all_pins[6]	4835114	1			T23	1		T24	185		T25	1
all_pins[7]	4835114	1			T23	1		T24	185		T25	1
all_pins[8]	4835114	1			T23	1		T24	185		T25	1
all_pins[9]	4835114	1			T23	1		T24	185		T25	1
all_pins[10]	4835114	1			T23	1		T24	185		T25	1
all_pins[11]	4835114	1			T23	1		T24	185		T25	1
all_pins[12]	4835114	1			T23	1		T24	185		T25	1
all_pins[13]	4835114	1			T23	1		T24	185		T25	1
all_pins[14]	4835114	1			T23	1		T24	185		T25	1
all_pins[15]	4835114	1			T23	1		T24	185		T25	1
all_pins[16]	4835114	1			T23	1		T24	185		T25	1
all_pins[17]	4835114	1			T23	1		T24	185		T25	1
all_pins[18]	4835114	1			T23	1		T24	185		T25	1
all_pins[19]	4835114	1			T23	1		T24	185		T25	1
all_pins[20]	4835114	1			T23	1		T24	185		T25	1
all_pins[21]	4835114	1			T23	1		T24	185		T25	1
all_pins[22]	4835114	1			T23	1		T24	185		T25	1
all_pins[23]	4835114	1			T23	1		T24	185		T25	1
all_pins[24]	4835114	1			T23	1		T24	185		T25	1
all_pins[25]	4835114	1			T23	1		T24	185		T25	1
all_pins[26]	4835114	1			T23	1		T24	185		T25	1
all_pins[27]	4835114	1			T23	1		T24	185		T25	1
all_pins[28]	4835114	1			T23	1		T24	185		T25	1
all_pins[29]	4835114	1			T23	1		T24	185		T25	1
all_pins[30]	4835114	1			T23	1		T24	185		T25	1
all_pins[31]	4835114	1			T23	1		T24	185		T25	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	96097025	1			T23	32		T24	3716		T25	32
values[0x1]	58626623	1			T24	2204		T26	2689		T27	8206
transitions[0x0=>0x1]	35133605	1			T24	1314		T26	1706		T27	5177
transitions[0x1=>0x0]	35133457	1			T24	1314		T26	1705		T27	5176

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3007368	1			T23	1		T24	104		T25	1
all_pins[0]	values[0x1]	1827746	1			T24	81		T26	85		T27	228
all_pins[0]	transitions[0x0=>0x1]	1132226	1			T24	61		T26	26		T27	156
all_pins[0]	transitions[0x1=>0x0]	1135931	1			T24	26		T26	76		T27	186
all_pins[1]	values[0x0]	3006953	1			T23	1		T24	111		T25	1
all_pins[1]	values[0x1]	1828161	1			T24	74		T26	80		T27	264
all_pins[1]	transitions[0x0=>0x1]	1097692	1			T24	43		T26	53		T27	169
all_pins[1]	transitions[0x1=>0x0]	1097277	1			T24	50		T26	58		T27	133
all_pins[2]	values[0x0]	3003660	1			T23	1		T24	110		T25	1
all_pins[2]	values[0x1]	1831454	1			T24	75		T26	69		T27	262
all_pins[2]	transitions[0x0=>0x1]	1097313	1			T24	46		T26	39		T27	170
all_pins[2]	transitions[0x1=>0x0]	1094020	1			T24	45		T26	50		T27	172
all_pins[3]	values[0x0]	3000911	1			T23	1		T24	101		T25	1
all_pins[3]	values[0x1]	1834203	1			T24	84		T26	67		T27	259
all_pins[3]	transitions[0x0=>0x1]	1098150	1			T24	47		T26	53		T27	152
all_pins[3]	transitions[0x1=>0x0]	1095401	1			T24	38		T26	55		T27	155
all_pins[4]	values[0x0]	2998861	1			T23	1		T24	134		T25	1
all_pins[4]	values[0x1]	1836253	1			T24	51		T26	69		T27	261
all_pins[4]	transitions[0x0=>0x1]	1100913	1			T24	23		T26	48		T27	146
all_pins[4]	transitions[0x1=>0x0]	1098863	1			T24	56		T26	46		T27	144
all_pins[5]	values[0x0]	3004431	1			T23	1		T24	138		T25	1
all_pins[5]	values[0x1]	1830683	1			T24	47		T26	57		T27	192
all_pins[5]	transitions[0x0=>0x1]	1095242	1			T24	33		T26	39		T27	120
all_pins[5]	transitions[0x1=>0x0]	1100812	1			T24	37		T26	51		T27	189
all_pins[6]	values[0x0]	3000746	1			T23	1		T24	133		T25	1
all_pins[6]	values[0x1]	1834368	1			T24	52		T26	63		T27	281
all_pins[6]	transitions[0x0=>0x1]	1098299	1			T24	34		T26	51		T27	222
all_pins[6]	transitions[0x1=>0x0]	1094614	1			T24	29		T26	45		T27	133
all_pins[7]	values[0x0]	3002684	1			T23	1		T24	127		T25	1
all_pins[7]	values[0x1]	1832430	1			T24	58		T26	32		T27	311
all_pins[7]	transitions[0x0=>0x1]	1094775	1			T24	35		T26	18		T27	193
all_pins[7]	transitions[0x1=>0x0]	1096713	1			T24	29		T26	49		T27	163
all_pins[8]	values[0x0]	3002017	1			T23	1		T24	139		T25	1
all_pins[8]	values[0x1]	1833097	1			T24	46		T26	59		T27	302
all_pins[8]	transitions[0x0=>0x1]	1095985	1			T24	21		T26	46		T27	152
all_pins[8]	transitions[0x1=>0x0]	1095318	1			T24	33		T26	19		T27	161
all_pins[9]	values[0x0]	2997576	1			T23	1		T24	111		T25	1
all_pins[9]	values[0x1]	1837538	1			T24	74		T26	99		T27	311
all_pins[9]	transitions[0x0=>0x1]	1102221	1			T24	52		T26	72		T27	183
all_pins[9]	transitions[0x1=>0x0]	1097780	1			T24	24		T26	32		T27	174
all_pins[10]	values[0x0]	3005058	1			T23	1		T24	115		T25	1
all_pins[10]	values[0x1]	1830056	1			T24	70		T26	87		T27	183
all_pins[10]	transitions[0x0=>0x1]	1093629	1			T24	33		T26	69		T27	100
all_pins[10]	transitions[0x1=>0x0]	1101111	1			T24	37		T26	81		T27	228
all_pins[11]	values[0x0]	3006049	1			T23	1		T24	116		T25	1
all_pins[11]	values[0x1]	1829065	1			T24	69		T26	67		T27	251
all_pins[11]	transitions[0x0=>0x1]	1094823	1			T24	52		T26	49		T27	217
all_pins[11]	transitions[0x1=>0x0]	1095814	1			T24	53		T26	69		T27	149
all_pins[12]	values[0x0]	3005828	1			T23	1		T24	109		T25	1
all_pins[12]	values[0x1]	1829286	1			T24	76		T26	121		T27	237
all_pins[12]	transitions[0x0=>0x1]	1095645	1			T24	50		T26	72		T27	168
all_pins[12]	transitions[0x1=>0x0]	1095424	1			T24	43		T26	18		T27	182
all_pins[13]	values[0x0]	3000041	1			T23	1		T24	102		T25	1
all_pins[13]	values[0x1]	1835073	1			T24	83		T26	118		T27	317
all_pins[13]	transitions[0x0=>0x1]	1098960	1			T24	57		T26	40		T27	195
all_pins[13]	transitions[0x1=>0x0]	1093173	1			T24	50		T26	43		T27	115
all_pins[14]	values[0x0]	3006077	1			T23	1		T24	111		T25	1
all_pins[14]	values[0x1]	1829037	1			T24	74		T26	120		T27	253
all_pins[14]	transitions[0x0=>0x1]	1093332	1			T24	38		T26	55		T27	119
all_pins[14]	transitions[0x1=>0x0]	1099368	1			T24	47		T26	53		T27	183
all_pins[15]	values[0x0]	3002147	1			T23	1		T24	86		T25	1
all_pins[15]	values[0x1]	1832967	1			T24	99		T26	94		T27	285
all_pins[15]	transitions[0x0=>0x1]	1100558	1			T24	57		T26	36		T27	189
all_pins[15]	transitions[0x1=>0x0]	1096628	1			T24	32		T26	62		T27	157
all_pins[16]	values[0x0]	3001789	1			T23	1		T24	108		T25	1
all_pins[16]	values[0x1]	1833325	1			T24	77		T26	116		T27	240
all_pins[16]	transitions[0x0=>0x1]	1095873	1			T24	29		T26	81		T27	125
all_pins[16]	transitions[0x1=>0x0]	1095515	1			T24	51		T26	59		T27	170
all_pins[17]	values[0x0]	3007006	1			T23	1		T24	128		T25	1
all_pins[17]	values[0x1]	1828108	1			T24	57		T26	48		T27	265
all_pins[17]	transitions[0x0=>0x1]	1094011	1			T24	27		T26	22		T27	196
all_pins[17]	transitions[0x1=>0x0]	1099228	1			T24	47		T26	90		T27	171
all_pins[18]	values[0x0]	2999416	1			T23	1		T24	144		T25	1
all_pins[18]	values[0x1]	1835698	1			T24	41		T26	106		T27	259
all_pins[18]	transitions[0x0=>0x1]	1098564	1			T24	30		T26	92		T27	141
all_pins[18]	transitions[0x1=>0x0]	1090974	1			T24	46		T26	34		T27	147
all_pins[19]	values[0x0]	3002402	1			T23	1		T24	114		T25	1
all_pins[19]	values[0x1]	1832712	1			T24	71		T26	86		T27	258
all_pins[19]	transitions[0x0=>0x1]	1094173	1			T24	52		T26	61		T27	170
all_pins[19]	transitions[0x1=>0x0]	1097159	1			T24	22		T26	81		T27	171
all_pins[20]	values[0x0]	2996947	1			T23	1		T24	93		T25	1
all_pins[20]	values[0x1]	1838167	1			T24	92		T26	79		T27	270
all_pins[20]	transitions[0x0=>0x1]	1100300	1			T24	58		T26	36		T27	179
all_pins[20]	transitions[0x1=>0x0]	1094845	1			T24	37		T26	43		T27	167
all_pins[21]	values[0x0]	3005022	1			T23	1		T24	117		T25	1
all_pins[21]	values[0x1]	1830092	1			T24	68		T26	78		T27	237
all_pins[21]	transitions[0x0=>0x1]	1093601	1			T24	31		T26	53		T27	145
all_pins[21]	transitions[0x1=>0x0]	1101676	1			T24	55		T26	54		T27	178
all_pins[22]	values[0x0]	3007064	1			T23	1		T24	106		T25	1
all_pins[22]	values[0x1]	1828050	1			T24	79		T26	122		T27	225
all_pins[22]	transitions[0x0=>0x1]	1095575	1			T24	51		T26	84		T27	146
all_pins[22]	transitions[0x1=>0x0]	1097617	1			T24	40		T26	40		T27	158
all_pins[23]	values[0x0]	3001319	1			T23	1		T24	135		T25	1
all_pins[23]	values[0x1]	1833795	1			T24	50		T26	97		T27	259
all_pins[23]	transitions[0x0=>0x1]	1099592	1			T24	26		T26	42		T27	166
all_pins[23]	transitions[0x1=>0x0]	1093847	1			T24	55		T26	67		T27	132
all_pins[24]	values[0x0]	3003508	1			T23	1		T24	113		T25	1
all_pins[24]	values[0x1]	1831606	1			T24	72		T26	64		T27	266
all_pins[24]	transitions[0x0=>0x1]	1095210	1			T24	52		T26	35		T27	171
all_pins[24]	transitions[0x1=>0x0]	1097399	1			T24	30		T26	68		T27	164
all_pins[25]	values[0x0]	2999498	1			T23	1		T24	125		T25	1
all_pins[25]	values[0x1]	1835616	1			T24	60		T26	85		T27	233
all_pins[25]	transitions[0x0=>0x1]	1100414	1			T24	28		T26	57		T27	147
all_pins[25]	transitions[0x1=>0x0]	1096404	1			T24	40		T26	36		T27	180
all_pins[26]	values[0x0]	3001766	1			T23	1		T24	109		T25	1
all_pins[26]	values[0x1]	1833348	1			T24	76		T26	69		T27	261
all_pins[26]	transitions[0x0=>0x1]	1094318	1			T24	61		T26	41		T27	181
all_pins[26]	transitions[0x1=>0x0]	1096586	1			T24	45		T26	57		T27	153
all_pins[27]	values[0x0]	3003569	1			T23	1		T24	90		T25	1
all_pins[27]	values[0x1]	1831545	1			T24	95		T26	97		T27	247
all_pins[27]	transitions[0x0=>0x1]	1095502	1			T24	44		T26	71		T27	122
all_pins[27]	transitions[0x1=>0x0]	1097305	1			T24	25		T26	43		T27	136
all_pins[28]	values[0x0]	3005185	1			T23	1		T24	126		T25	1
all_pins[28]	values[0x1]	1829929	1			T24	59		T26	59		T27	237
all_pins[28]	transitions[0x0=>0x1]	1094553	1			T24	22		T26	49		T27	146
all_pins[28]	transitions[0x1=>0x0]	1096169	1			T24	58		T26	87		T27	156
all_pins[29]	values[0x0]	3003162	1			T23	1		T24	122		T25	1
all_pins[29]	values[0x1]	1831952	1			T24	63		T26	55		T27	212
all_pins[29]	transitions[0x0=>0x1]	1097068	1			T24	40		T26	49		T27	117
all_pins[29]	transitions[0x1=>0x0]	1095045	1			T24	36		T26	53		T27	142
all_pins[30]	values[0x0]	3005450	1			T23	1		T24	100		T25	1
all_pins[30]	values[0x1]	1829664	1			T24	85		T26	105		T27	281
all_pins[30]	transitions[0x0=>0x1]	1096776	1			T24	58		T26	96		T27	217
all_pins[30]	transitions[0x1=>0x0]	1099064	1			T24	36		T26	46		T27	148
all_pins[31]	values[0x0]	3003515	1			T23	1		T24	139		T25	1
all_pins[31]	values[0x1]	1831599	1			T24	46		T26	136		T27	259
all_pins[31]	transitions[0x0=>0x1]	1098312	1			T24	23		T26	71		T27	157
all_pins[31]	transitions[0x1=>0x0]	1096377	1			T24	62		T26	40		T27	179