Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	15786883	1			T23	153		T24	329		T25	292
all_values[1]	15786883	1			T23	153		T24	329		T25	292
all_values[2]	15786883	1			T23	153		T24	329		T25	292
all_values[3]	15786883	1			T23	153		T24	329		T25	292
all_values[4]	15786883	1			T23	153		T24	329		T25	292
all_values[5]	15786883	1			T23	153		T24	329		T25	292
all_values[6]	15786883	1			T23	153		T24	329		T25	292
all_values[7]	15786883	1			T23	153		T24	329		T25	292
all_values[8]	15786883	1			T23	153		T24	329		T25	292
all_values[9]	15786883	1			T23	153		T24	329		T25	292
all_values[10]	15786883	1			T23	153		T24	329		T25	292
all_values[11]	15786883	1			T23	153		T24	329		T25	292
all_values[12]	15786883	1			T23	153		T24	329		T25	292
all_values[13]	15786883	1			T23	153		T24	329		T25	292
all_values[14]	15786883	1			T23	153		T24	329		T25	292
all_values[15]	15786883	1			T23	153		T24	329		T25	292
all_values[16]	15786883	1			T23	153		T24	329		T25	292
all_values[17]	15786883	1			T23	153		T24	329		T25	292
all_values[18]	15786883	1			T23	153		T24	329		T25	292
all_values[19]	15786883	1			T23	153		T24	329		T25	292
all_values[20]	15786883	1			T23	153		T24	329		T25	292
all_values[21]	15786883	1			T23	153		T24	329		T25	292
all_values[22]	15786883	1			T23	153		T24	329		T25	292
all_values[23]	15786883	1			T23	153		T24	329		T25	292
all_values[24]	15786883	1			T23	153		T24	329		T25	292
all_values[25]	15786883	1			T23	153		T24	329		T25	292
all_values[26]	15786883	1			T23	153		T24	329		T25	292
all_values[27]	15786883	1			T23	153		T24	329		T25	292
all_values[28]	15786883	1			T23	153		T24	329		T25	292
all_values[29]	15786883	1			T23	153		T24	329		T25	292
all_values[30]	15786883	1			T23	153		T24	329		T25	292
all_values[31]	15786883	1			T23	153		T24	329		T25	292

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

286929960

1

T23

4896

T24

5440

T25

9344

auto[1]

218250296

1

T24

5088

T26

10948

T27

27897

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

110782395

1

T23

4896

T24

1798

T25

9344

auto[1]

394397861

1

T24

8730

T26

20516

T27

50141

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

499596432

1

T23

4896

T24

10528

T25

9344

auto[1]

5583824

1

T27

2015

T32

43011

T45

2278

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2807404	1			T23	153		T24	16		T25	292
all_values[0]	auto[0]	auto[0]	auto[1]	6077708	1			T24	105		T26	288		T27	818
all_values[0]	auto[0]	auto[1]	auto[0]	669513	1			T24	44		T26	43		T27	144
all_values[0]	auto[0]	auto[1]	auto[1]	6057245	1			T24	164		T26	354		T27	617
all_values[0]	auto[1]	auto[0]	auto[1]	87562	1			T27	31		T32	663		T45	32
all_values[0]	auto[1]	auto[1]	auto[1]	87451	1			T27	32		T32	679		T45	25
all_values[1]	auto[0]	auto[0]	auto[0]	2811646	1			T23	153		T24	18		T25	292
all_values[1]	auto[0]	auto[0]	auto[1]	6065917	1			T24	140		T26	323		T27	828
all_values[1]	auto[0]	auto[1]	auto[0]	666581	1			T24	28		T26	56		T27	111
all_values[1]	auto[0]	auto[1]	auto[1]	6068447	1			T24	143		T26	291		T27	709
all_values[1]	auto[1]	auto[0]	auto[1]	87806	1			T27	36		T32	722		T45	34
all_values[1]	auto[1]	auto[1]	auto[1]	86486	1			T27	29		T32	634		T45	30
all_values[2]	auto[0]	auto[0]	auto[0]	2804151	1			T23	153		T24	30		T25	292
all_values[2]	auto[0]	auto[0]	auto[1]	6119250	1			T24	115		T26	330		T27	662
all_values[2]	auto[0]	auto[1]	auto[0]	658501	1			T24	36		T26	43		T27	158
all_values[2]	auto[0]	auto[1]	auto[1]	6030204	1			T24	148		T26	310		T27	764
all_values[2]	auto[1]	auto[0]	auto[1]	87267	1			T27	34		T32	638		T45	37
all_values[2]	auto[1]	auto[1]	auto[1]	87510	1			T27	31		T32	668		T45	37
all_values[3]	auto[0]	auto[0]	auto[0]	2797762	1			T23	153		T24	23		T25	292
all_values[3]	auto[0]	auto[0]	auto[1]	6059544	1			T24	123		T26	409		T27	727
all_values[3]	auto[0]	auto[1]	auto[0]	659764	1			T24	19		T26	1		T27	143
all_values[3]	auto[0]	auto[1]	auto[1]	6095798	1			T24	164		T26	254		T27	776
all_values[3]	auto[1]	auto[0]	auto[1]	87625	1			T27	31		T32	651		T45	42
all_values[3]	auto[1]	auto[1]	auto[1]	86390	1			T27	39		T32	690		T45	33
all_values[4]	auto[0]	auto[0]	auto[0]	2793345	1			T23	153		T24	40		T25	292
all_values[4]	auto[0]	auto[0]	auto[1]	6069859	1			T24	174		T26	413		T27	684
all_values[4]	auto[0]	auto[1]	auto[0]	656062	1			T24	12		T26	45		T27	119
all_values[4]	auto[0]	auto[1]	auto[1]	6093297	1			T24	103		T26	224		T27	783
all_values[4]	auto[1]	auto[0]	auto[1]	87297	1			T27	23		T32	650		T45	50
all_values[4]	auto[1]	auto[1]	auto[1]	87023	1			T27	44		T32	658		T45	26
all_values[5]	auto[0]	auto[0]	auto[0]	2811808	1			T23	153		T24	57		T25	292
all_values[5]	auto[0]	auto[0]	auto[1]	6102804	1			T24	137		T26	406		T27	934
all_values[5]	auto[0]	auto[1]	auto[0]	659823	1			T24	40		T26	35		T27	58
all_values[5]	auto[0]	auto[1]	auto[1]	6038475	1			T24	95		T26	216		T27	591
all_values[5]	auto[1]	auto[0]	auto[1]	87223	1			T27	39		T32	657		T45	30
all_values[5]	auto[1]	auto[1]	auto[1]	86750	1			T27	21		T32	720		T45	33
all_values[6]	auto[0]	auto[0]	auto[0]	2798721	1			T23	153		T24	36		T25	292
all_values[6]	auto[0]	auto[0]	auto[1]	6069085	1			T24	146		T26	415		T27	818
all_values[6]	auto[0]	auto[1]	auto[0]	660229	1			T24	41		T26	16		T27	74
all_values[6]	auto[0]	auto[1]	auto[1]	6084164	1			T24	106		T26	254		T27	777
all_values[6]	auto[1]	auto[0]	auto[1]	87038	1			T27	40		T32	638		T45	34
all_values[6]	auto[1]	auto[1]	auto[1]	87646	1			T27	24		T32	674		T45	33
all_values[7]	auto[0]	auto[0]	auto[0]	2800721	1			T23	153		T24	35		T25	292
all_values[7]	auto[0]	auto[0]	auto[1]	6035525	1			T24	147		T26	466		T27	694
all_values[7]	auto[0]	auto[1]	auto[0]	660278	1			T24	25		T26	30		T27	97
all_values[7]	auto[0]	auto[1]	auto[1]	6115762	1			T24	122		T26	145		T27	894
all_values[7]	auto[1]	auto[0]	auto[1]	87413	1			T27	25		T32	707		T45	38
all_values[7]	auto[1]	auto[1]	auto[1]	87184	1			T27	34		T32	645		T45	36
all_values[8]	auto[0]	auto[0]	auto[0]	2789222	1			T23	153		T24	37		T25	292
all_values[8]	auto[0]	auto[0]	auto[1]	6061278	1			T24	172		T26	456		T27	634
all_values[8]	auto[0]	auto[1]	auto[0]	645867	1			T24	18		T26	10		T27	117
all_values[8]	auto[0]	auto[1]	auto[1]	6115536	1			T24	102		T26	195		T27	868
all_values[8]	auto[1]	auto[0]	auto[1]	87638	1			T27	20		T32	710		T45	36
all_values[8]	auto[1]	auto[1]	auto[1]	87342	1			T27	43		T32	640		T45	39
all_values[9]	auto[0]	auto[0]	auto[0]	2799516	1			T23	153		T24	37		T25	292
all_values[9]	auto[0]	auto[0]	auto[1]	6064170	1			T24	137		T26	183		T27	542
all_values[9]	auto[0]	auto[1]	auto[0]	661086	1			T24	12		T26	86		T27	156
all_values[9]	auto[0]	auto[1]	auto[1]	6087518	1			T24	143		T26	410		T27	945
all_values[9]	auto[1]	auto[0]	auto[1]	87174	1			T27	27		T32	679		T45	36
all_values[9]	auto[1]	auto[1]	auto[1]	87419	1			T27	37		T32	678		T45	25
all_values[10]	auto[0]	auto[0]	auto[0]	2804561	1			T23	153		T24	19		T25	292
all_values[10]	auto[0]	auto[0]	auto[1]	6083080	1			T24	157		T26	350		T27	942
all_values[10]	auto[0]	auto[1]	auto[0]	655957	1			T24	13		T26	10		T27	132
all_values[10]	auto[0]	auto[1]	auto[1]	6069144	1			T24	140		T26	314		T27	529
all_values[10]	auto[1]	auto[0]	auto[1]	87092	1			T27	38		T32	665		T45	38
all_values[10]	auto[1]	auto[1]	auto[1]	87049	1			T27	26		T32	707		T45	42
all_values[11]	auto[0]	auto[0]	auto[0]	2807770	1			T23	153		T24	36		T25	292
all_values[11]	auto[0]	auto[0]	auto[1]	6072520	1			T24	143		T26	398		T27	797
all_values[11]	auto[0]	auto[1]	auto[0]	668624	1			T24	9		T26	38		T27	125
all_values[11]	auto[0]	auto[1]	auto[1]	6063418	1			T24	141		T26	227		T27	674
all_values[11]	auto[1]	auto[0]	auto[1]	87451	1			T27	39		T32	698		T45	34
all_values[11]	auto[1]	auto[1]	auto[1]	87100	1			T27	25		T32	645		T45	44
all_values[12]	auto[0]	auto[0]	auto[0]	2800488	1			T23	153		T24	46		T25	292
all_values[12]	auto[0]	auto[0]	auto[1]	6081396	1			T24	123		T26	221		T27	791
all_values[12]	auto[0]	auto[1]	auto[0]	667770	1			T24	11		T26	16		T27	91
all_values[12]	auto[0]	auto[1]	auto[1]	6062481	1			T24	149		T26	447		T27	726
all_values[12]	auto[1]	auto[0]	auto[1]	87728	1			T27	31		T32	687		T45	43
all_values[12]	auto[1]	auto[1]	auto[1]	87020	1			T27	34		T32	634		T45	30
all_values[13]	auto[0]	auto[0]	auto[0]	2791329	1			T23	153		T24	14		T25	292
all_values[13]	auto[0]	auto[0]	auto[1]	6094933	1			T24	152		T26	204		T27	736
all_values[13]	auto[0]	auto[1]	auto[0]	664477	1			T24	15		T26	21		T27	98
all_values[13]	auto[0]	auto[1]	auto[1]	6061952	1			T24	148		T26	422		T27	815
all_values[13]	auto[1]	auto[0]	auto[1]	87474	1			T27	30		T32	666		T45	33
all_values[13]	auto[1]	auto[1]	auto[1]	86718	1			T27	26		T32	701		T45	40
all_values[14]	auto[0]	auto[0]	auto[0]	2798992	1			T23	153		T24	30		T25	292
all_values[14]	auto[0]	auto[0]	auto[1]	6071172	1			T24	117		T26	265		T27	734
all_values[14]	auto[0]	auto[1]	auto[0]	664640	1			T24	39		T26	36		T27	127
all_values[14]	auto[0]	auto[1]	auto[1]	6077898	1			T24	143		T26	396		T27	750
all_values[14]	auto[1]	auto[0]	auto[1]	87033	1			T27	31		T32	639		T45	38
all_values[14]	auto[1]	auto[1]	auto[1]	87148	1			T27	29		T32	715		T45	28
all_values[15]	auto[0]	auto[0]	auto[0]	2800570	1			T23	153		T24	16		T25	292
all_values[15]	auto[0]	auto[0]	auto[1]	6072395	1			T24	98		T26	313		T27	677
all_values[15]	auto[0]	auto[1]	auto[0]	653814	1			T24	31		T26	34		T27	143
all_values[15]	auto[0]	auto[1]	auto[1]	6085191	1			T24	184		T26	339		T27	807
all_values[15]	auto[1]	auto[0]	auto[1]	87454	1			T27	29		T32	719		T45	35
all_values[15]	auto[1]	auto[1]	auto[1]	87459	1			T27	37		T32	613		T45	35
all_values[16]	auto[0]	auto[0]	auto[0]	2798633	1			T23	153		T24	13		T25	292
all_values[16]	auto[0]	auto[0]	auto[1]	6075901	1			T24	130		T26	150		T27	797
all_values[16]	auto[0]	auto[1]	auto[0]	659820	1			T24	34		T26	27		T27	99
all_values[16]	auto[0]	auto[1]	auto[1]	6077588	1			T24	152		T26	492		T27	701
all_values[16]	auto[1]	auto[0]	auto[1]	87402	1			T27	37		T32	674		T45	35
all_values[16]	auto[1]	auto[1]	auto[1]	87539	1			T27	27		T32	677		T45	33
all_values[17]	auto[0]	auto[0]	auto[0]	2806482	1			T23	153		T24	35		T25	292
all_values[17]	auto[0]	auto[0]	auto[1]	6097099	1			T24	145		T26	469		T27	812
all_values[17]	auto[0]	auto[1]	auto[0]	650075	1			T24	39		T26	18		T27	86
all_values[17]	auto[0]	auto[1]	auto[1]	6058640	1			T24	110		T26	199		T27	765
all_values[17]	auto[1]	auto[0]	auto[1]	87620	1			T27	32		T32	686		T45	28
all_values[17]	auto[1]	auto[1]	auto[1]	86967	1			T27	24		T32	637		T45	43
all_values[18]	auto[0]	auto[0]	auto[0]	2811127	1			T23	153		T24	46		T25	292
all_values[18]	auto[0]	auto[0]	auto[1]	6066473	1			T24	165		T26	234		T27	878
all_values[18]	auto[0]	auto[1]	auto[0]	665711	1			T24	34		T26	12		T27	60
all_values[18]	auto[0]	auto[1]	auto[1]	6069286	1			T24	84		T26	427		T27	706
all_values[18]	auto[1]	auto[0]	auto[1]	87229	1			T27	30		T32	735		T45	33
all_values[18]	auto[1]	auto[1]	auto[1]	87057	1			T27	24		T32	622		T45	36
all_values[19]	auto[0]	auto[0]	auto[0]	2806800	1			T23	153		T24	30		T25	292
all_values[19]	auto[0]	auto[0]	auto[1]	6086450	1			T24	115		T26	314		T27	862
all_values[19]	auto[0]	auto[1]	auto[0]	654561	1			T24	45		T26	42		T27	92
all_values[19]	auto[0]	auto[1]	auto[1]	6064606	1			T24	139		T26	306		T27	697
all_values[19]	auto[1]	auto[0]	auto[1]	87181	1			T27	31		T32	735		T45	42
all_values[19]	auto[1]	auto[1]	auto[1]	87285	1			T27	30		T32	629		T45	26
all_values[20]	auto[0]	auto[0]	auto[0]	2798359	1			T23	153		T24	24		T25	292
all_values[20]	auto[0]	auto[0]	auto[1]	6071603	1			T24	110		T26	349		T27	808
all_values[20]	auto[0]	auto[1]	auto[0]	661082	1			T24	16		T26	23		T27	80
all_values[20]	auto[0]	auto[1]	auto[1]	6081381	1			T24	179		T26	317		T27	768
all_values[20]	auto[1]	auto[0]	auto[1]	87042	1			T27	36		T32	646		T45	39
all_values[20]	auto[1]	auto[1]	auto[1]	87416	1			T27	23		T32	685		T45	34
all_values[21]	auto[0]	auto[0]	auto[0]	2793502	1			T23	153		T24	24		T25	292
all_values[21]	auto[0]	auto[0]	auto[1]	6099227	1			T24	184		T26	312		T27	932
all_values[21]	auto[0]	auto[1]	auto[0]	668482	1			T24	11		T26	30		T27	40
all_values[21]	auto[0]	auto[1]	auto[1]	6051414	1			T24	110		T26	354		T27	671
all_values[21]	auto[1]	auto[0]	auto[1]	87616	1			T27	38		T32	634		T45	33
all_values[21]	auto[1]	auto[1]	auto[1]	86642	1			T27	25		T32	695		T45	32
all_values[22]	auto[0]	auto[0]	auto[0]	2788916	1			T23	153		T24	14		T25	292
all_values[22]	auto[0]	auto[0]	auto[1]	6099763	1			T24	155		T26	290		T27	925
all_values[22]	auto[0]	auto[1]	auto[0]	657729	1			T24	10		T26	16		T27	132
all_values[22]	auto[0]	auto[1]	auto[1]	6066074	1			T24	150		T26	385		T27	558
all_values[22]	auto[1]	auto[0]	auto[1]	87803	1			T27	34		T32	677		T45	24
all_values[22]	auto[1]	auto[1]	auto[1]	86598	1			T27	30		T32	687		T45	40
all_values[23]	auto[0]	auto[0]	auto[0]	2800308	1			T23	153		T24	44		T25	292
all_values[23]	auto[0]	auto[0]	auto[1]	6076433	1			T24	158		T26	255		T27	706
all_values[23]	auto[0]	auto[1]	auto[0]	669294	1			T24	22		T26	26		T27	92
all_values[23]	auto[0]	auto[1]	auto[1]	6066147	1			T24	105		T26	407		T27	797
all_values[23]	auto[1]	auto[0]	auto[1]	87625	1			T27	28		T32	695		T45	41
all_values[23]	auto[1]	auto[1]	auto[1]	87076	1			T27	30		T32	658		T45	40
all_values[24]	auto[0]	auto[0]	auto[0]	2796593	1			T23	153		T24	31		T25	292
all_values[24]	auto[0]	auto[0]	auto[1]	6076700	1			T24	149		T26	269		T27	751
all_values[24]	auto[0]	auto[1]	auto[0]	665134	1			T24	21		T26	56		T27	179
all_values[24]	auto[0]	auto[1]	auto[1]	6074201	1			T24	128		T26	281		T27	687
all_values[24]	auto[1]	auto[0]	auto[1]	87006	1			T27	31		T32	690		T45	50
all_values[24]	auto[1]	auto[1]	auto[1]	87249	1			T27	43		T32	678		T45	27
all_values[25]	auto[0]	auto[0]	auto[0]	2800329	1			T23	153		T24	31		T25	292
all_values[25]	auto[0]	auto[0]	auto[1]	6068467	1			T24	169		T26	324		T27	833
all_values[25]	auto[0]	auto[1]	auto[0]	655270	1			T24	11		T26	8		T27	55
all_values[25]	auto[0]	auto[1]	auto[1]	6087885	1			T24	118		T26	286		T27	692
all_values[25]	auto[1]	auto[0]	auto[1]	87189	1			T27	32		T32	680		T45	36
all_values[25]	auto[1]	auto[1]	auto[1]	87743	1			T27	23		T32	696		T45	43
all_values[26]	auto[0]	auto[0]	auto[0]	2795181	1			T23	153		T24	34		T25	292
all_values[26]	auto[0]	auto[0]	auto[1]	6080018	1			T24	109		T26	359		T27	727
all_values[26]	auto[0]	auto[1]	auto[0]	666171	1			T24	23		T26	42		T27	126
all_values[26]	auto[0]	auto[1]	auto[1]	6070878	1			T24	163		T26	243		T27	769
all_values[26]	auto[1]	auto[0]	auto[1]	87308	1			T27	33		T32	687		T45	45
all_values[26]	auto[1]	auto[1]	auto[1]	87327	1			T27	43		T32	681		T45	29
all_values[27]	auto[0]	auto[0]	auto[0]	2794921	1			T23	153		T24	23		T25	292
all_values[27]	auto[0]	auto[0]	auto[1]	6099517	1			T24	99		T26	294		T27	721
all_values[27]	auto[0]	auto[1]	auto[0]	661366	1			T24	20		T26	4		T27	189
all_values[27]	auto[0]	auto[1]	auto[1]	6056523	1			T24	187		T26	337		T27	678
all_values[27]	auto[1]	auto[0]	auto[1]	87253	1			T27	33		T32	687		T45	43
all_values[27]	auto[1]	auto[1]	auto[1]	87303	1			T27	33		T32	642		T45	35
all_values[28]	auto[0]	auto[0]	auto[0]	2801917	1			T23	153		T24	61		T25	292
all_values[28]	auto[0]	auto[0]	auto[1]	6077683	1			T24	125		T26	418		T27	878
all_values[28]	auto[0]	auto[1]	auto[0]	662243	1			T24	27		T26	25		T27	78
all_values[28]	auto[0]	auto[1]	auto[1]	6071023	1			T24	116		T26	241		T27	639
all_values[28]	auto[1]	auto[0]	auto[1]	87153	1			T27	39		T32	715		T45	24
all_values[28]	auto[1]	auto[1]	auto[1]	86864	1			T27	24		T32	650		T45	37
all_values[29]	auto[0]	auto[0]	auto[0]	2800424	1			T23	153		T24	40		T25	292
all_values[29]	auto[0]	auto[0]	auto[1]	6089357	1			T24	138		T26	492		T27	891
all_values[29]	auto[0]	auto[1]	auto[0]	663258	1			T24	40		T26	7		T27	126
all_values[29]	auto[0]	auto[1]	auto[1]	6059040	1			T24	111		T26	163		T27	546
all_values[29]	auto[1]	auto[0]	auto[1]	87925	1			T27	47		T32	734		T45	48
all_values[29]	auto[1]	auto[1]	auto[1]	86879	1			T27	17		T32	609		T45	25
all_values[30]	auto[0]	auto[0]	auto[0]	2806170	1			T23	153		T24	22		T25	292
all_values[30]	auto[0]	auto[0]	auto[1]	6075264	1			T24	111		T26	301		T27	678
all_values[30]	auto[0]	auto[1]	auto[0]	663721	1			T24	22		T26	31		T27	121
all_values[30]	auto[0]	auto[1]	auto[1]	6067372	1			T24	174		T26	361		T27	808
all_values[30]	auto[1]	auto[0]	auto[1]	87296	1			T27	22		T32	636		T45	50
all_values[30]	auto[1]	auto[1]	auto[1]	87060	1			T27	37		T32	676		T45	28
all_values[31]	auto[0]	auto[0]	auto[0]	2800759	1			T23	153		T24	59		T25	292
all_values[31]	auto[0]	auto[0]	auto[1]	6074453	1			T24	171		T26	208		T27	661
all_values[31]	auto[0]	auto[1]	auto[0]	667065	1			T24	9		T26	23		T27	218
all_values[31]	auto[0]	auto[1]	auto[1]	6070405	1			T24	90		T26	441		T27	741
all_values[31]	auto[1]	auto[0]	auto[1]	87566	1			T27	25		T32	670		T45	34
all_values[31]	auto[1]	auto[1]	auto[1]	86635	1			T27	39		T32	618		T45	39

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal