Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[1]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[2]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[3]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[4]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[5]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[6]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[7]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[8]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[9]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[10]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[11]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[12]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[13]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[14]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[15]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[16]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[17]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[18]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[19]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[20]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[21]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[22]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[23]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[24]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[25]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[26]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[27]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[28]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[29]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[30]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[31]	15521252	1			T23	213		T24	173		T25	570

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299706363

1

T23

4372

T24

2787

T25

4271

auto[1]

196973701

1

T23

2444

T24

2749

T25

13969

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

397154176

1

T23

4893

T24

5536

T25

13737

auto[1]

99525888

1

T23

1923

T25

4503

T27

23729

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

368013946

1

T23

5018

T24

5536

T25

9611

auto[1]

128666118

1

T23

1798

T25

8629

T27

27827

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5773475	1			T23	67		T24	78		T25	30
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	4164033	1			T23	53		T24	95		T25	138
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1563801	1			T23	30		T25	74		T27	415
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	2019315	1			T23	25		T25	31		T27	471
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	449874	1			T25	168		T27	23		T31	16
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1550754	1			T23	38		T25	129		T27	290
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5792060	1			T23	88		T24	103		T25	26
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	4147601	1			T23	42		T24	70		T25	177
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1563852	1			T23	24		T25	109		T27	446
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	2025114	1			T23	23		T25	36		T27	410
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	448269	1			T25	173		T27	26		T31	12
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1544356	1			T23	36		T25	49		T27	354
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5795874	1			T23	71		T24	82		T25	46
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	4152835	1			T23	55		T24	91		T25	209
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1561295	1			T23	39		T25	110		T27	380
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	2016861	1			T23	18		T25	17		T27	465
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	449966	1			T25	121		T27	29		T31	12
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1544421	1			T23	30		T25	67		T27	309
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5789238	1			T23	82		T24	92		T25	24
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	4149199	1			T23	53		T24	81		T25	177
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1571537	1			T23	34		T25	88		T27	352
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	2015202	1			T23	22		T25	33		T27	501
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	446765	1			T25	179		T27	23		T31	28
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1549311	1			T23	22		T25	69		T27	413
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5774476	1			T23	79		T24	75		T25	35
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	4157454	1			T23	47		T24	98		T25	185
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1563383	1			T23	32		T25	78		T27	317
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	2019277	1			T23	34		T25	29		T27	596
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	451451	1			T25	172		T27	25		T31	16
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1555211	1			T23	21		T25	71		T27	313
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5783123	1			T23	63		T24	97		T25	41
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	4153702	1			T23	53		T24	76		T25	242
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1563336	1			T23	26		T25	56		T27	357
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	2018132	1			T23	36		T25	19		T27	544
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	449354	1			T25	157		T27	31		T31	22
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1553605	1			T23	35		T25	55		T27	441
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5783960	1			T23	71		T24	79		T25	18
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	4153525	1			T23	49		T24	94		T25	177
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1563886	1			T23	45		T25	73		T27	425
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	2021649	1			T23	20		T25	43		T27	398
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	447424	1			T25	205		T27	9		T31	3
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1550808	1			T23	28		T25	54		T27	292
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5777982	1			T23	75		T24	85		T25	22
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	4146096	1			T23	41		T24	88		T25	199
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1558477	1			T23	42		T25	90		T27	298
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	2028983	1			T23	29		T25	20		T27	534
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	452198	1			T25	172		T27	21		T31	14
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1557516	1			T23	26		T25	67		T27	397
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5776819	1			T23	94		T24	79		T25	21
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	4158472	1			T23	45		T24	94		T25	194
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1567685	1			T23	18		T25	63		T27	449
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	2021716	1			T23	34		T25	34		T27	408
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	448861	1			T25	206		T27	20		T31	16
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1547699	1			T23	22		T25	52		T27	335
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5774334	1			T23	73		T24	85		T25	33
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	4153544	1			T23	50		T24	88		T25	226
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1567752	1			T23	30		T25	70		T27	369
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	2023635	1			T23	34		T25	12		T27	521
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	449911	1			T25	133		T27	21		T31	37
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1552076	1			T23	26		T25	96		T27	268
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5778018	1			T23	72		T24	78		T25	15
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	4154263	1			T23	56		T24	95		T25	119
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1569055	1			T23	33		T25	87		T27	435
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	2016972	1			T23	36		T25	48		T27	374
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	447843	1			T25	216		T27	18		T31	16
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1555101	1			T23	16		T25	85		T27	405
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5775083	1			T23	69		T24	89		T25	53
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	4165249	1			T23	57		T24	84		T25	234
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1566859	1			T23	32		T25	55		T27	327
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	2013872	1			T23	23		T25	9		T27	517
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	450062	1			T25	181		T27	16		T31	25
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1550127	1			T23	32		T25	38		T27	452
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5769896	1			T23	71		T24	85		T25	32
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	4164325	1			T23	56		T24	88		T25	249
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1561829	1			T23	14		T25	79		T27	361
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	2023044	1			T23	46		T25	18		T27	496
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	449314	1			T25	120		T27	22		T31	12
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1552844	1			T23	26		T25	72		T27	377
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5763580	1			T23	80		T24	97		T25	43
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	4173480	1			T23	44		T24	76		T25	260
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1568206	1			T23	22		T25	89		T27	305
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	2012764	1			T23	20		T25	17		T27	490
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	450862	1			T25	137		T27	35		T31	12
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1552360	1			T23	47		T25	24		T27	464
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5780099	1			T23	97		T24	93		T25	29
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	4162719	1			T23	32		T24	80		T25	216
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1564146	1			T23	36		T25	79		T27	333
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	2020207	1			T23	20		T25	21		T27	535
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	449665	1			T25	179		T27	16		T31	16
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1544416	1			T23	28		T25	46		T27	393
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5781187	1			T23	66		T24	84		T25	27
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	4153658	1			T23	54		T24	89		T25	150
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1560882	1			T23	25		T25	47		T27	400
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	2021805	1			T23	40		T25	31		T27	515
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	449807	1			T25	225		T27	20		T31	26
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1553913	1			T23	28		T25	90		T27	327
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5784359	1			T23	92		T24	71		T25	32
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	4157744	1			T23	40		T24	102		T25	204
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1558140	1			T23	25		T25	57		T27	381
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	2024127	1			T23	24		T25	39		T27	461
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	449202	1			T25	185		T27	31		T31	27
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1547680	1			T23	32		T25	53		T27	365
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5779214	1			T23	63		T24	100		T25	32
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	4155136	1			T23	58		T24	73		T25	153
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1556639	1			T23	44		T25	65		T27	447
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	2033890	1			T23	28		T25	34		T27	450
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	452773	1			T25	198		T27	16		T31	24
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1543600	1			T23	20		T25	88		T27	379
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5779704	1			T23	114		T24	104		T25	34
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	4166069	1			T23	42		T24	69		T25	188
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1564078	1			T23	25		T25	65		T27	329
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	2021692	1			T23	28		T25	20		T27	510
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	448975	1			T25	207		T27	22		T31	4
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1540734	1			T23	4		T25	56		T27	441
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5771376	1			T23	73		T24	86		T25	30
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	4167950	1			T23	49		T24	87		T25	139
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1563521	1			T23	32		T25	58		T27	370
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	2023904	1			T23	22		T25	28		T27	400
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	451046	1			T25	215		T27	21		T31	25
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1543455	1			T23	37		T25	100		T27	391
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5782330	1			T23	86		T24	83		T25	26
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	4157549	1			T23	46		T24	90		T25	193
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1558145	1			T23	26		T25	106		T27	412
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	2028244	1			T23	32		T25	35		T27	390
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	450634	1			T25	154		T27	14		T31	21
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1544350	1			T23	23		T25	56		T27	352
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5778609	1			T23	68		T24	91		T25	49
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	4167848	1			T23	48		T24	82		T25	243
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1560828	1			T23	37		T25	67		T27	352
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	2021770	1			T23	16		T25	20		T27	527
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	446347	1			T25	99		T27	24		T31	30
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1545850	1			T23	44		T25	92		T27	462
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5788824	1			T23	69		T24	80		T25	29
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	4152843	1			T23	55		T24	93		T25	190
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1560437	1			T23	34		T25	79		T27	382
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	2022093	1			T23	24		T25	18		T27	494
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	451803	1			T25	213		T27	30		T31	23
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1545252	1			T23	31		T25	41		T27	333
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5797023	1			T23	75		T24	77		T25	43
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	4149083	1			T23	44		T24	96		T25	246
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1554934	1			T23	34		T25	83		T27	386
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	2023596	1			T23	26		T25	23		T27	461
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	450310	1			T25	107		T27	20		T31	20
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1546306	1			T23	34		T25	68		T27	323
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5780298	1			T23	80		T24	83		T25	49
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	4156705	1			T23	42		T24	90		T25	250
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1560501	1			T23	28		T25	78		T27	347
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	2021369	1			T23	26		T25	18		T27	497
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	450624	1			T25	141		T27	16		T31	19
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1551755	1			T23	37		T25	34		T27	377
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5779684	1			T23	73		T24	92		T25	28
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	4160099	1			T23	49		T24	81		T25	151
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1559040	1			T23	47		T25	82		T27	371
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	2027851	1			T23	22		T25	34		T27	421
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	448949	1			T25	206		T27	36		T31	4
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1545629	1			T23	22		T25	69		T27	402
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5779532	1			T23	66		T24	93		T25	27
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	4153136	1			T23	42		T24	80		T25	178
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1560254	1			T23	41		T25	79		T27	271
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	2030844	1			T23	40		T25	30		T27	616
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	453459	1			T25	190		T27	35		T31	10
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1544027	1			T23	24		T25	66		T27	351
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5789888	1			T23	58		T24	89		T25	24
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	4146994	1			T23	54		T24	84		T25	163
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1555482	1			T23	34		T25	69		T27	325
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	2035949	1			T23	28		T25	27		T27	509
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	449439	1			T25	206		T27	20		T31	9
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1543500	1			T23	39		T25	81		T27	342
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5785935	1			T23	65		T24	89		T25	24
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	4154264	1			T23	53		T24	84		T25	138
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1554725	1			T23	39		T25	43		T27	328
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	2025532	1			T23	38		T25	40		T27	508
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	454221	1			T25	246		T27	17		T31	15
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1546575	1			T23	18		T25	79		T27	365
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5777756	1			T23	96		T24	103		T25	33
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	4161942	1			T23	44		T24	70		T25	158
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1561840	1			T23	38		T25	70		T27	456
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	2018910	1			T23	25		T25	29		T27	422
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	451859	1			T25	206		T27	10		T31	19
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1548945	1			T23	10		T25	74		T27	324
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5787558	1			T23	73		T24	82		T25	33
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	4158755	1			T23	51		T24	91		T25	261
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1562600	1			T23	34		T25	68		T27	460
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	2020152	1			T23	32		T25	27		T27	342
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	448724	1			T25	144		T27	20		T31	20
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1543463	1			T23	23		T25	37		T27	370
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5785561	1			T23	60		T24	83		T25	32
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	4156660	1			T23	51		T24	90		T25	204
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1557014	1			T23	34		T25	64		T27	337
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	2026878	1			T23	38		T25	31		T27	529
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	449049	1			T25	174		T27	22		T31	18
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1546090	1			T23	30		T25	65		T27	399

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal