Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[1]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[2]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[3]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[4]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[5]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[6]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[7]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[8]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[9]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[10]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[11]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[12]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[13]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[14]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[15]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[16]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[17]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[18]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[19]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[20]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[21]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[22]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[23]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[24]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[25]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[26]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[27]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[28]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[29]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[30]	15521252	1			T23	213		T24	173		T25	570
bins_for_gpio_bits[31]	15521252	1			T23	213		T24	173		T25	570

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299706363

1

T23

4372

T24

2787

T25

4271

auto[1]

196973701

1

T23

2444

T24

2749

T25

13969

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299699041

1

T23

4363

T24

2787

T25

4279

auto[1]

196981023

1

T23

2453

T24

2749

T25

13961

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	9078306	1			T23	115		T24	78		T25	120
bins_for_gpio_bits[0]	auto[0]	auto[1]	278042	1			T23	7		T25	15		T27	52
bins_for_gpio_bits[0]	auto[1]	auto[0]	278285	1			T23	7		T25	15		T27	52
bins_for_gpio_bits[0]	auto[1]	auto[1]	5886619	1			T23	84		T24	95		T25	420
bins_for_gpio_bits[1]	auto[0]	auto[0]	9103010	1			T23	128		T24	103		T25	159
bins_for_gpio_bits[1]	auto[0]	auto[1]	277767	1			T23	7		T25	13		T27	50
bins_for_gpio_bits[1]	auto[1]	auto[0]	278016	1			T23	7		T25	12		T27	50
bins_for_gpio_bits[1]	auto[1]	auto[1]	5862459	1			T23	71		T24	70		T25	386
bins_for_gpio_bits[2]	auto[0]	auto[0]	9095992	1			T23	121		T24	82		T25	154
bins_for_gpio_bits[2]	auto[0]	auto[1]	277832	1			T23	7		T25	19		T27	49
bins_for_gpio_bits[2]	auto[1]	auto[0]	278038	1			T23	7		T25	19		T27	49
bins_for_gpio_bits[2]	auto[1]	auto[1]	5869390	1			T23	78		T24	91		T25	378
bins_for_gpio_bits[3]	auto[0]	auto[0]	9097426	1			T23	131		T24	92		T25	131
bins_for_gpio_bits[3]	auto[0]	auto[1]	278341	1			T23	7		T25	14		T27	62
bins_for_gpio_bits[3]	auto[1]	auto[0]	278551	1			T23	7		T25	14		T27	62
bins_for_gpio_bits[3]	auto[1]	auto[1]	5866934	1			T23	68		T24	81		T25	411
bins_for_gpio_bits[4]	auto[0]	auto[0]	9078697	1			T23	139		T24	75		T25	128
bins_for_gpio_bits[4]	auto[0]	auto[1]	278240	1			T23	5		T25	14		T27	52
bins_for_gpio_bits[4]	auto[1]	auto[0]	278439	1			T23	6		T25	14		T27	52
bins_for_gpio_bits[4]	auto[1]	auto[1]	5885876	1			T23	63		T24	98		T25	414
bins_for_gpio_bits[5]	auto[0]	auto[0]	9086157	1			T23	118		T24	97		T25	105
bins_for_gpio_bits[5]	auto[0]	auto[1]	278224	1			T23	6		T25	11		T27	62
bins_for_gpio_bits[5]	auto[1]	auto[0]	278434	1			T23	7		T25	11		T27	62
bins_for_gpio_bits[5]	auto[1]	auto[1]	5878437	1			T23	82		T24	76		T25	443
bins_for_gpio_bits[6]	auto[0]	auto[0]	9091477	1			T23	130		T24	79		T25	121
bins_for_gpio_bits[6]	auto[0]	auto[1]	277804	1			T23	6		T25	13		T27	53
bins_for_gpio_bits[6]	auto[1]	auto[0]	278018	1			T23	6		T25	13		T27	53
bins_for_gpio_bits[6]	auto[1]	auto[1]	5873953	1			T23	71		T24	94		T25	423
bins_for_gpio_bits[7]	auto[0]	auto[0]	9086596	1			T23	138		T24	85		T25	116
bins_for_gpio_bits[7]	auto[0]	auto[1]	278598	1			T23	8		T25	16		T27	50
bins_for_gpio_bits[7]	auto[1]	auto[0]	278846	1			T23	8		T25	16		T27	50
bins_for_gpio_bits[7]	auto[1]	auto[1]	5877212	1			T23	59		T24	88		T25	422
bins_for_gpio_bits[8]	auto[0]	auto[0]	9087668	1			T23	138		T24	79		T25	108
bins_for_gpio_bits[8]	auto[0]	auto[1]	278330	1			T23	8		T25	11		T27	50
bins_for_gpio_bits[8]	auto[1]	auto[0]	278552	1			T23	8		T25	10		T27	50
bins_for_gpio_bits[8]	auto[1]	auto[1]	5876702	1			T23	59		T24	94		T25	441
bins_for_gpio_bits[9]	auto[0]	auto[0]	9087365	1			T23	132		T24	85		T25	102
bins_for_gpio_bits[9]	auto[0]	auto[1]	278086	1			T23	5		T25	14		T27	43
bins_for_gpio_bits[9]	auto[1]	auto[0]	278356	1			T23	5		T25	13		T27	43
bins_for_gpio_bits[9]	auto[1]	auto[1]	5877445	1			T23	71		T24	88		T25	441
bins_for_gpio_bits[10]	auto[0]	auto[0]	9085118	1			T23	136		T24	78		T25	136
bins_for_gpio_bits[10]	auto[0]	auto[1]	278691	1			T23	5		T25	15		T27	50
bins_for_gpio_bits[10]	auto[1]	auto[0]	278927	1			T23	5		T25	14		T27	50
bins_for_gpio_bits[10]	auto[1]	auto[1]	5878516	1			T23	67		T24	95		T25	405
bins_for_gpio_bits[11]	auto[0]	auto[0]	9077406	1			T23	115		T24	89		T25	103
bins_for_gpio_bits[11]	auto[0]	auto[1]	278174	1			T23	9		T25	14		T27	55
bins_for_gpio_bits[11]	auto[1]	auto[0]	278408	1			T23	9		T25	14		T27	55
bins_for_gpio_bits[11]	auto[1]	auto[1]	5887264	1			T23	80		T24	84		T25	439
bins_for_gpio_bits[12]	auto[0]	auto[0]	9075770	1			T23	124		T24	85		T25	112
bins_for_gpio_bits[12]	auto[0]	auto[1]	278763	1			T23	7		T25	18		T27	54
bins_for_gpio_bits[12]	auto[1]	auto[0]	278999	1			T23	7		T25	17		T27	54
bins_for_gpio_bits[12]	auto[1]	auto[1]	5887720	1			T23	75		T24	88		T25	423
bins_for_gpio_bits[13]	auto[0]	auto[0]	9065850	1			T23	114		T24	97		T25	133
bins_for_gpio_bits[13]	auto[0]	auto[1]	278443	1			T23	7		T25	16		T27	53
bins_for_gpio_bits[13]	auto[1]	auto[0]	278700	1			T23	8		T25	16		T27	53
bins_for_gpio_bits[13]	auto[1]	auto[1]	5898259	1			T23	84		T24	76		T25	405
bins_for_gpio_bits[14]	auto[0]	auto[0]	9086936	1			T23	147		T24	93		T25	115
bins_for_gpio_bits[14]	auto[0]	auto[1]	277303	1			T23	6		T25	14		T27	52
bins_for_gpio_bits[14]	auto[1]	auto[0]	277516	1			T23	6		T25	14		T27	52
bins_for_gpio_bits[14]	auto[1]	auto[1]	5879497	1			T23	54		T24	80		T25	427
bins_for_gpio_bits[15]	auto[0]	auto[0]	9085957	1			T23	125		T24	84		T25	97
bins_for_gpio_bits[15]	auto[0]	auto[1]	277729	1			T23	6		T25	8		T27	52
bins_for_gpio_bits[15]	auto[1]	auto[0]	277917	1			T23	6		T25	8		T27	52
bins_for_gpio_bits[15]	auto[1]	auto[1]	5879649	1			T23	76		T24	89		T25	457
bins_for_gpio_bits[16]	auto[0]	auto[0]	9088431	1			T23	135		T24	71		T25	115
bins_for_gpio_bits[16]	auto[0]	auto[1]	277956	1			T23	6		T25	14		T27	50
bins_for_gpio_bits[16]	auto[1]	auto[0]	278195	1			T23	6		T25	13		T27	50
bins_for_gpio_bits[16]	auto[1]	auto[1]	5876670	1			T23	66		T24	102		T25	428
bins_for_gpio_bits[17]	auto[0]	auto[0]	9091539	1			T23	129		T24	100		T25	115
bins_for_gpio_bits[17]	auto[0]	auto[1]	277988	1			T23	6		T25	16		T27	65
bins_for_gpio_bits[17]	auto[1]	auto[0]	278204	1			T23	6		T25	16		T27	65
bins_for_gpio_bits[17]	auto[1]	auto[1]	5873521	1			T23	72		T24	73		T25	423
bins_for_gpio_bits[18]	auto[0]	auto[0]	9087966	1			T23	165		T24	104		T25	108
bins_for_gpio_bits[18]	auto[0]	auto[1]	277266	1			T23	2		T25	11		T27	56
bins_for_gpio_bits[18]	auto[1]	auto[0]	277508	1			T23	2		T25	11		T27	56
bins_for_gpio_bits[18]	auto[1]	auto[1]	5878512	1			T23	44		T24	69		T25	440
bins_for_gpio_bits[19]	auto[0]	auto[0]	9080435	1			T23	117		T24	86		T25	105
bins_for_gpio_bits[19]	auto[0]	auto[1]	278146	1			T23	9		T25	11		T27	54
bins_for_gpio_bits[19]	auto[1]	auto[0]	278366	1			T23	10		T25	11		T27	54
bins_for_gpio_bits[19]	auto[1]	auto[1]	5884305	1			T23	77		T24	87		T25	443
bins_for_gpio_bits[20]	auto[0]	auto[0]	9090636	1			T23	138		T24	83		T25	150
bins_for_gpio_bits[20]	auto[0]	auto[1]	277839	1			T23	5		T25	17		T27	46
bins_for_gpio_bits[20]	auto[1]	auto[0]	278083	1			T23	6		T25	17		T27	46
bins_for_gpio_bits[20]	auto[1]	auto[1]	5874694	1			T23	64		T24	90		T25	386
bins_for_gpio_bits[21]	auto[0]	auto[0]	9082718	1			T23	113		T24	91		T25	123
bins_for_gpio_bits[21]	auto[0]	auto[1]	278273	1			T23	8		T25	13		T27	62
bins_for_gpio_bits[21]	auto[1]	auto[0]	278489	1			T23	8		T25	13		T27	62
bins_for_gpio_bits[21]	auto[1]	auto[1]	5881772	1			T23	84		T24	82		T25	421
bins_for_gpio_bits[22]	auto[0]	auto[0]	9093136	1			T23	120		T24	80		T25	112
bins_for_gpio_bits[22]	auto[0]	auto[1]	277971	1			T23	6		T25	14		T27	51
bins_for_gpio_bits[22]	auto[1]	auto[0]	278218	1			T23	7		T25	14		T27	51
bins_for_gpio_bits[22]	auto[1]	auto[1]	5871927	1			T23	80		T24	93		T25	430
bins_for_gpio_bits[23]	auto[0]	auto[0]	9097768	1			T23	127		T24	77		T25	133
bins_for_gpio_bits[23]	auto[0]	auto[1]	277579	1			T23	8		T25	16		T27	50
bins_for_gpio_bits[23]	auto[1]	auto[0]	277785	1			T23	8		T25	16		T27	50
bins_for_gpio_bits[23]	auto[1]	auto[1]	5868120	1			T23	70		T24	96		T25	405
bins_for_gpio_bits[24]	auto[0]	auto[0]	9083645	1			T23	125		T24	83		T25	131
bins_for_gpio_bits[24]	auto[0]	auto[1]	278285	1			T23	8		T25	14		T27	51
bins_for_gpio_bits[24]	auto[1]	auto[0]	278523	1			T23	9		T25	14		T27	51
bins_for_gpio_bits[24]	auto[1]	auto[1]	5880799	1			T23	71		T24	90		T25	411
bins_for_gpio_bits[25]	auto[0]	auto[0]	9088070	1			T23	136		T24	92		T25	129
bins_for_gpio_bits[25]	auto[0]	auto[1]	278270	1			T23	6		T25	15		T27	54
bins_for_gpio_bits[25]	auto[1]	auto[0]	278505	1			T23	6		T25	15		T27	54
bins_for_gpio_bits[25]	auto[1]	auto[1]	5876407	1			T23	65		T24	81		T25	411
bins_for_gpio_bits[26]	auto[0]	auto[0]	9092065	1			T23	139		T24	93		T25	123
bins_for_gpio_bits[26]	auto[0]	auto[1]	278348	1			T23	8		T25	13		T27	50
bins_for_gpio_bits[26]	auto[1]	auto[0]	278565	1			T23	8		T25	13		T27	50
bins_for_gpio_bits[26]	auto[1]	auto[1]	5872274	1			T23	58		T24	80		T25	421
bins_for_gpio_bits[27]	auto[0]	auto[0]	9102664	1			T23	110		T24	89		T25	109
bins_for_gpio_bits[27]	auto[0]	auto[1]	278422	1			T23	9		T25	12		T27	56
bins_for_gpio_bits[27]	auto[1]	auto[0]	278655	1			T23	10		T25	11		T27	56
bins_for_gpio_bits[27]	auto[1]	auto[1]	5861511	1			T23	84		T24	84		T25	438
bins_for_gpio_bits[28]	auto[0]	auto[0]	9087944	1			T23	136		T24	89		T25	98
bins_for_gpio_bits[28]	auto[0]	auto[1]	278011	1			T23	6		T25	9		T27	53
bins_for_gpio_bits[28]	auto[1]	auto[0]	278248	1			T23	6		T25	9		T27	53
bins_for_gpio_bits[28]	auto[1]	auto[1]	5877049	1			T23	65		T24	84		T25	454
bins_for_gpio_bits[29]	auto[0]	auto[0]	9080540	1			T23	156		T24	103		T25	118
bins_for_gpio_bits[29]	auto[0]	auto[1]	277716	1			T23	3		T25	14		T27	40
bins_for_gpio_bits[29]	auto[1]	auto[0]	277966	1			T23	3		T25	14		T27	40
bins_for_gpio_bits[29]	auto[1]	auto[1]	5885030	1			T23	51		T24	70		T25	424
bins_for_gpio_bits[30]	auto[0]	auto[0]	9092197	1			T23	129		T24	82		T25	120
bins_for_gpio_bits[30]	auto[0]	auto[1]	277886	1			T23	9		T25	9		T27	52
bins_for_gpio_bits[30]	auto[1]	auto[0]	278113	1			T23	10		T25	8		T27	52
bins_for_gpio_bits[30]	auto[1]	auto[1]	5873056	1			T23	65		T24	91		T25	433
bins_for_gpio_bits[31]	auto[0]	auto[0]	9091524	1			T23	124		T24	83		T25	116
bins_for_gpio_bits[31]	auto[0]	auto[1]	277709	1			T23	8		T25	11		T27	52
bins_for_gpio_bits[31]	auto[1]	auto[0]	277929	1			T23	8		T25	11		T27	52
bins_for_gpio_bits[31]	auto[1]	auto[1]	5874090	1			T23	73		T24	90		T25	432