Unified Coverage Report :: Group Instance : intr_event_falling_pin26

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8972674

1

T23

153

T24

121

T25

292

auto[1]

6814209

1

T24

208

T26

397

T27

793

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14915724

1

T23

153

T24

315

T25

292

auto[1]

871159

1

T24

14

T26

41

T27

48

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8991794

1

T23

153

T24

133

T25

292

auto[1]

6795089

1

T24

196

T26

189

T27

1055

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2969192

1

T24

64

T26

78

T27

561

auto[1]

auto[0]

auto[1]

437109

1

T24

3

T26

22

T27

27

auto[1]

auto[1]

auto[0]

2954738

1

T24

118

T26

70

T27

446

auto[1]

auto[1]

auto[1]

434050

1

T24

11

T26

19

T27

21

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8965369

1

T23

153

T24

158

T25

292

auto[1]

6821514

1

T24

171

T26

347

T27

849

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14910363

1

T23

153

T24

318

T25

292

auto[1]

876520

1

T24

11

T26

61

T27

44

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8974324

1

T23

153

T24

113

T25

292

auto[1]

6812559

1

T24

216

T26

275

T27

918

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2977570

1

T24

113

T26

85

T27

476

auto[1]

auto[0]

auto[1]

439433

1

T24

7

T26

26

T27

30

auto[1]

auto[1]

auto[0]

2958469

1

T24

92

T26

129

T27

398

auto[1]

auto[1]

auto[1]

437087

1

T24

4

T26

35

T27

14

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8974733

1

T23

153

T24

176

T25

292

auto[1]

6812150

1

T24

153

T26

324

T27

687

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14915642

1

T23

153

T24

321

T25

292

auto[1]

871241

1

T24

8

T26

51

T27

27

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9001762

1

T23

153

T24

161

T25

292

auto[1]

6785121

1

T24

168

T26

267

T27

858

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2958679

1

T24

92

T26

62

T27

468

auto[1]

auto[0]

auto[1]

436019

1

T24

3

T26

11

T27

14

auto[1]

auto[1]

auto[0]

2955201

1

T24

68

T26

154

T27

363

auto[1]

auto[1]

auto[1]

435222

1

T24

5

T26

40

T27

13

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8967741

1

T23

153

T24

179

T25

292

auto[1]

6819142

1

T24

150

T26

265

T27

824

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14911082

1

T23

153

T24

319

T25

292

auto[1]

875801

1

T24

10

T26

80

T27

37

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8974811

1

T23

153

T24

166

T25

292

auto[1]

6812072

1

T24

163

T26

423

T27

837

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2966126

1

T24

100

T26

205

T27

476

auto[1]

auto[0]

auto[1]

437395

1

T24

5

T26

46

T27

24

auto[1]

auto[1]

auto[0]

2970145

1

T24

53

T26

138

T27

324

auto[1]

auto[1]

auto[1]

438406

1

T24

5

T26

34

T27

13

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8969612

1

T23

153

T24

169

T25

292

auto[1]

6817271

1

T24

160

T26

463

T27

851

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14907137

1

T23

153

T24

321

T25

292

auto[1]

879746

1

T24

8

T26

62

T27

35

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8952758

1

T23

153

T24

192

T25

292

auto[1]

6834125

1

T24

137

T26

306

T27

916

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2973226

1

T24

49

T26

78

T27

468

auto[1]

auto[0]

auto[1]

438948

1

T24

5

T26

19

T27

16

auto[1]

auto[1]

auto[0]

2981153

1

T24

80

T26

166

T27

413

auto[1]

auto[1]

auto[1]

440798

1

T24

3

T26

43

T27

19

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8973736

1

T23

153

T24

166

T25

292

auto[1]

6813147

1

T24

163

T26

443

T27

939

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14910996

1

T23

153

T24

320

T25

292

auto[1]

875887

1

T24

9

T26

67

T27

34

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8971057

1

T23

153

T24

195

T25

292

auto[1]

6815826

1

T24

134

T26

353

T27

819

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2963265

1

T24

74

T26

56

T27

336

auto[1]

auto[0]

auto[1]

437141

1

T24

5

T26

16

T27

12

auto[1]

auto[1]

auto[0]

2976674

1

T24

51

T26

230

T27

449

auto[1]

auto[1]

auto[1]

438746

1

T24

4

T26

51

T27

22

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8957197

1

T23

153

T24

147

T25

292

auto[1]

6829686

1

T24

182

T26

432

T27

906

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14908445

1

T23

153

T24

318

T25

292

auto[1]

878438

1

T24

11

T26

77

T27

35

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8956524

1

T23

153

T24

156

T25

292

auto[1]

6830359

1

T24

173

T26

350

T27

862

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2971166

1

T24

70

T26

84

T27

440

auto[1]

auto[0]

auto[1]

438609

1

T24

2

T26

25

T27

18

auto[1]

auto[1]

auto[0]

2980755

1

T24

92

T26

189

T27

387

auto[1]

auto[1]

auto[1]

439829

1

T24

9

T26

52

T27

17

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8960419

1

T23

153

T24

114

T25

292

auto[1]

6826464

1

T24

215

T26

373

T27

987

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14909905

1

T23

153

T24

315

T25

292

auto[1]

876978

1

T24

14

T26

68

T27

41

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8962107

1

T23

153

T24

169

T25

292

auto[1]

6824776

1

T24

160

T26

351

T27

894

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2968012

1

T24

48

T26

227

T27

389

auto[1]

auto[0]

auto[1]

437655

1

T24

3

T26

57

T27

20

auto[1]

auto[1]

auto[0]

2979786

1

T24

98

T26

56

T27

464

auto[1]

auto[1]

auto[1]

439323

1

T24

11

T26

11

T27

21

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8961936

1

T23

153

T24

143

T25

292

auto[1]

6824947

1

T24

186

T26

519

T27

827

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14911360

1

T23

153

T24

321

T25

292

auto[1]

875523

1

T24

8

T26

105

T27

38

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8970936

1

T23

153

T24

141

T25

292

auto[1]

6815947

1

T24

188

T26

518

T27

933

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2977857

1

T24

74

T26

51

T27

521

auto[1]

auto[0]

auto[1]

439693

1

T24

2

T26

12

T27

19

auto[1]

auto[1]

auto[0]

2962567

1

T24

106

T26

362

T27

374

auto[1]

auto[1]

auto[1]

435830

1

T24

6

T26

93

T27

19

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8991201

1

T23

153

T24

180

T25

292

auto[1]

6795682

1

T24

149

T26

217

T27

875

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14915091

1

T23

153

T24

325

T25

292

auto[1]

871792

1

T24

4

T26

24

T27

42

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8988194

1

T23

153

T24

212

T25

292

auto[1]

6798689

1

T24

117

T26

139

T27

793

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2971105

1

T24

63

T26

88

T27

366

auto[1]

auto[0]

auto[1]

437268

1

T26

20

T27

22

T32

3187

auto[1]

auto[1]

auto[0]

2955792

1

T24

50

T26

27

T27

385

auto[1]

auto[1]

auto[1]

434524

1

T24

4

T26

4

T27

20

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8964829

1

T23

153

T24

211

T25

292

auto[1]

6822054

1

T24

118

T26

439

T27

790

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14915461

1

T23

153

T24

322

T25

292

auto[1]

871422

1

T24

7

T26

91

T27

28

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8983077

1

T23

153

T24

204

T25

292

auto[1]

6803806

1

T24

125

T26

453

T27

742

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2959234

1

T24

68

T26

155

T27

418

auto[1]

auto[0]

auto[1]

434523

1

T24

4

T26

42

T27

13

auto[1]

auto[1]

auto[0]

2973150

1

T24

50

T26

207

T27

296

auto[1]

auto[1]

auto[1]

436899

1

T24

3

T26

49

T27

15

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8980431

1

T23

153

T24

145

T25

292

auto[1]

6806452

1

T24

184

T26

348

T27

819

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14911559

1

T23

153

T24

323

T25

292

auto[1]

875324

1

T24

6

T26

66

T27

50

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8970237

1

T23

153

T24

199

T25

292

auto[1]

6816646

1

T24

130

T26

312

T27

994

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2970359

1

T24

42

T26

94

T27

524

auto[1]

auto[0]

auto[1]

438609

1

T24

2

T26

24

T27

24

auto[1]

auto[1]

auto[0]

2970963

1

T24

82

T26

152

T27

420

auto[1]

auto[1]

auto[1]

436715

1

T24

4

T26

42

T27

26

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9010668

1

T23

153

T24

145

T25

292

auto[1]

6776215

1

T24

184

T26

353

T27

953

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14911106

1

T23

153

T24

315

T25

292

auto[1]

875777

1

T24

14

T26

47

T27

35

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8967192

1

T23

153

T24

141

T25

292

auto[1]

6819691

1

T24

188

T26

243

T27

929

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2993326

1

T24

80

T26

64

T27

455

auto[1]

auto[0]

auto[1]

442885

1

T24

7

T26

13

T27

19

auto[1]

auto[1]

auto[0]

2950588

1

T24

94

T26

132

T27

439

auto[1]

auto[1]

auto[1]

432892

1

T24

7

T26

34

T27

16

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8957004

1

T23

153

T24

134

T25

292

auto[1]

6829879

1

T24

195

T26

340

T27

871

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14909686

1

T23

153

T24

321

T25

292

auto[1]

877197

1

T24

8

T26

103

T27

40

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8954891

1

T23

153

T24

202

T25

292

auto[1]

6831992

1

T24

127

T26

535

T27

1116

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2973191

1

T24

45

T26

220

T27

531

auto[1]

auto[0]

auto[1]

437807

1

T24

4

T26

48

T27

16

auto[1]

auto[1]

auto[0]

2981604

1

T24

74

T26

212

T27

545

auto[1]

auto[1]

auto[1]

439390

1

T24

4

T26

55

T27

24

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8980345

1

T23

153

T24

208

T25

292

auto[1]

6806538

1

T24

121

T26

384

T27

736

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14916213

1

T23

153

T24

311

T25

292

auto[1]

870670

1

T24

18

T26

73

T27

51

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8995836

1

T23

153

T24

111

T25

292

auto[1]

6791047

1

T24

218

T26

347

T27

929

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2975598

1

T24

127

T26

172

T27

541

auto[1]

auto[0]

auto[1]

437979

1

T24

12

T26

42

T27

31

auto[1]

auto[1]

auto[0]

2944779

1

T24

73

T26

102

T27

337

auto[1]

auto[1]

auto[1]

432691

1

T24

6

T26

31

T27

20

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8976482

1

T23

153

T24

169

T25

292

auto[1]

6810401

1

T24

160

T26

401

T27

720

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14906061

1

T23

153

T24

318

T25

292

auto[1]

880822

1

T24

11

T26

93

T27

31

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8935817

1

T23

153

T24

188

T25

292

auto[1]

6851066

1

T24

141

T26

455

T27

865

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2995720

1

T24

55

T26

153

T27

522

auto[1]

auto[0]

auto[1]

442822

1

T24

5

T26

39

T27

23

auto[1]

auto[1]

auto[0]

2974524

1

T24

75

T26

209

T27

312

auto[1]

auto[1]

auto[1]

438000

1

T24

6

T26

54

T27

8

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8964366

1

T23

153

T24

202

T25

292

auto[1]

6822517

1

T24

127

T26

433

T27

919

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14911356

1

T23

153

T24

312

T25

292

auto[1]

875527

1

T24

17

T26

44

T27

30

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8960559

1

T23

153

T24

97

T25

292

auto[1]

6826324

1

T24

232

T26

249

T27

885

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2976763

1

T24

122

T26

85

T27

417

auto[1]

auto[0]

auto[1]

437906

1

T24

9

T26

22

T27

17

auto[1]

auto[1]

auto[0]

2974034

1

T24

93

T26

120

T27

438

auto[1]

auto[1]

auto[1]

437621

1

T24

8

T26

22

T27

13

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8960299

1

T23

153

T24

180

T25

292

auto[1]

6826584

1

T24

149

T26

337

T27

909

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14913110

1

T23

153

T24

318

T25

292

auto[1]

873773

1

T24

11

T26

28

T27

31

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8975143

1

T23

153

T24

172

T25

292

auto[1]

6811740

1

T24

157

T26

165

T27

833

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2979138

1

T24

70

T26

81

T27

425

auto[1]

auto[0]

auto[1]

439135

1

T24

4

T26

17

T27

15

auto[1]

auto[1]

auto[0]

2958829

1

T24

76

T26

56

T27

377

auto[1]

auto[1]

auto[1]

434638

1

T24

7

T26

11

T27

16

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8955985

1

T23

153

T24

200

T25

292

auto[1]

6830898

1

T24

129

T26

294

T27

770

---

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14912632

1

T23

153

T24

323

T25

292

auto[1]

874251

1

T24

6

T26

43

T27

39

---

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8980437

1

T23

153

T24

207

T25

292

auto[1]

6806446

1

T24

122

T26

204

T27

748

---

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

auto[0]

2962275

1

T24

67

T26

49

T27

374

auto[1]

auto[0]

auto[1]

436742

1

T24

3

T26

10

T27

18

auto[1]

auto[1]

auto[0]

2969920

1

T24

49

T26

112

T27

335

auto[1]

auto[1]

auto[1]

437509

1

T24

3

T26

33

T27

21

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8962507

1

T23

153

T24

143

T25

292

auto[1]

6824376

1

T24

186

T26

285

T27

938