Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9001835 |
1 |
|
|
T23 |
153 |
|
T24 |
194 |
|
T25 |
292 |
| auto[1] |
6785048 |
1 |
|
|
T24 |
135 |
|
T26 |
251 |
|
T27 |
670 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14919755 |
1 |
|
|
T23 |
153 |
|
T24 |
319 |
|
T25 |
292 |
| auto[1] |
867128 |
1 |
|
|
T24 |
10 |
|
T26 |
21 |
|
T27 |
37 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9018193 |
1 |
|
|
T23 |
153 |
|
T24 |
191 |
|
T25 |
292 |
| auto[1] |
6768690 |
1 |
|
|
T24 |
138 |
|
T26 |
109 |
|
T27 |
781 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2973593 |
1 |
|
|
T24 |
74 |
|
T26 |
50 |
|
T27 |
500 |
| auto[1] |
auto[0] |
auto[1] |
437501 |
1 |
|
|
T24 |
5 |
|
T26 |
12 |
|
T27 |
25 |
| auto[1] |
auto[1] |
auto[0] |
2927969 |
1 |
|
|
T24 |
54 |
|
T26 |
38 |
|
T27 |
244 |
| auto[1] |
auto[1] |
auto[1] |
429627 |
1 |
|
|
T24 |
5 |
|
T26 |
9 |
|
T27 |
12 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |