Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8954844 |
1 |
|
|
T23 |
153 |
|
T24 |
182 |
|
T25 |
292 |
| auto[1] |
6832039 |
1 |
|
|
T24 |
147 |
|
T26 |
270 |
|
T27 |
875 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14909091 |
1 |
|
|
T23 |
153 |
|
T24 |
319 |
|
T25 |
292 |
| auto[1] |
877792 |
1 |
|
|
T24 |
10 |
|
T26 |
69 |
|
T27 |
39 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8953258 |
1 |
|
|
T23 |
153 |
|
T24 |
115 |
|
T25 |
292 |
| auto[1] |
6833625 |
1 |
|
|
T24 |
214 |
|
T26 |
352 |
|
T27 |
980 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2969760 |
1 |
|
|
T24 |
87 |
|
T26 |
206 |
|
T27 |
521 |
| auto[1] |
auto[0] |
auto[1] |
437296 |
1 |
|
|
T24 |
4 |
|
T26 |
45 |
|
T27 |
24 |
| auto[1] |
auto[1] |
auto[0] |
2986073 |
1 |
|
|
T24 |
117 |
|
T26 |
77 |
|
T27 |
420 |
| auto[1] |
auto[1] |
auto[1] |
440496 |
1 |
|
|
T24 |
6 |
|
T26 |
24 |
|
T27 |
15 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |