Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8923659 |
1 |
|
|
T23 |
153 |
|
T24 |
182 |
|
T25 |
292 |
| auto[1] |
6863224 |
1 |
|
|
T24 |
147 |
|
T26 |
175 |
|
T27 |
1025 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14911357 |
1 |
|
|
T23 |
153 |
|
T24 |
319 |
|
T25 |
292 |
| auto[1] |
875526 |
1 |
|
|
T24 |
10 |
|
T26 |
63 |
|
T27 |
36 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8974512 |
1 |
|
|
T23 |
153 |
|
T24 |
189 |
|
T25 |
292 |
| auto[1] |
6812371 |
1 |
|
|
T24 |
140 |
|
T26 |
347 |
|
T27 |
892 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2949775 |
1 |
|
|
T24 |
76 |
|
T26 |
189 |
|
T27 |
361 |
| auto[1] |
auto[0] |
auto[1] |
435229 |
1 |
|
|
T24 |
5 |
|
T26 |
43 |
|
T27 |
11 |
| auto[1] |
auto[1] |
auto[0] |
2987070 |
1 |
|
|
T24 |
54 |
|
T26 |
95 |
|
T27 |
495 |
| auto[1] |
auto[1] |
auto[1] |
440297 |
1 |
|
|
T24 |
5 |
|
T26 |
20 |
|
T27 |
25 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |