Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8938138 |
1 |
|
|
T23 |
153 |
|
T24 |
209 |
|
T25 |
292 |
| auto[1] |
6848745 |
1 |
|
|
T24 |
120 |
|
T26 |
205 |
|
T27 |
1028 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14902608 |
1 |
|
|
T23 |
153 |
|
T24 |
314 |
|
T25 |
292 |
| auto[1] |
884275 |
1 |
|
|
T24 |
15 |
|
T26 |
56 |
|
T27 |
28 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8912015 |
1 |
|
|
T23 |
153 |
|
T24 |
150 |
|
T25 |
292 |
| auto[1] |
6874868 |
1 |
|
|
T24 |
179 |
|
T26 |
295 |
|
T27 |
779 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2995850 |
1 |
|
|
T24 |
112 |
|
T26 |
183 |
|
T27 |
311 |
| auto[1] |
auto[0] |
auto[1] |
442171 |
1 |
|
|
T24 |
8 |
|
T26 |
44 |
|
T27 |
12 |
| auto[1] |
auto[1] |
auto[0] |
2994743 |
1 |
|
|
T24 |
52 |
|
T26 |
56 |
|
T27 |
440 |
| auto[1] |
auto[1] |
auto[1] |
442104 |
1 |
|
|
T24 |
7 |
|
T26 |
12 |
|
T27 |
16 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |