Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8950860 |
1 |
|
|
T23 |
153 |
|
T24 |
174 |
|
T25 |
292 |
| auto[1] |
6836023 |
1 |
|
|
T24 |
155 |
|
T26 |
496 |
|
T27 |
1138 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14911502 |
1 |
|
|
T23 |
153 |
|
T24 |
324 |
|
T25 |
292 |
| auto[1] |
875381 |
1 |
|
|
T24 |
5 |
|
T26 |
47 |
|
T27 |
26 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8968082 |
1 |
|
|
T23 |
153 |
|
T24 |
209 |
|
T25 |
292 |
| auto[1] |
6818801 |
1 |
|
|
T24 |
120 |
|
T26 |
240 |
|
T27 |
707 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2969676 |
1 |
|
|
T24 |
55 |
|
T26 |
49 |
|
T27 |
252 |
| auto[1] |
auto[0] |
auto[1] |
437628 |
1 |
|
|
T24 |
2 |
|
T26 |
9 |
|
T27 |
9 |
| auto[1] |
auto[1] |
auto[0] |
2973744 |
1 |
|
|
T24 |
60 |
|
T26 |
144 |
|
T27 |
429 |
| auto[1] |
auto[1] |
auto[1] |
437753 |
1 |
|
|
T24 |
3 |
|
T26 |
38 |
|
T27 |
17 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |