Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8972674 |
1 |
|
|
T23 |
153 |
|
T24 |
121 |
|
T25 |
292 |
| auto[1] |
6814209 |
1 |
|
|
T24 |
208 |
|
T26 |
397 |
|
T27 |
793 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13010203 |
1 |
|
|
T23 |
153 |
|
T24 |
247 |
|
T25 |
292 |
| auto[1] |
2776680 |
1 |
|
|
T24 |
82 |
|
T26 |
155 |
|
T27 |
129 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8972670 |
1 |
|
|
T23 |
153 |
|
T24 |
180 |
|
T25 |
292 |
| auto[1] |
6814213 |
1 |
|
|
T24 |
149 |
|
T26 |
320 |
|
T27 |
788 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2016572 |
1 |
|
|
T24 |
31 |
|
T26 |
43 |
|
T27 |
412 |
| auto[1] |
auto[0] |
auto[1] |
1386583 |
1 |
|
|
T24 |
26 |
|
T26 |
45 |
|
T27 |
74 |
| auto[1] |
auto[1] |
auto[0] |
2020961 |
1 |
|
|
T24 |
36 |
|
T26 |
122 |
|
T27 |
247 |
| auto[1] |
auto[1] |
auto[1] |
1390097 |
1 |
|
|
T24 |
56 |
|
T26 |
110 |
|
T27 |
55 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |