Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8965369 |
1 |
|
|
T23 |
153 |
|
T24 |
158 |
|
T25 |
292 |
| auto[1] |
6821514 |
1 |
|
|
T24 |
171 |
|
T26 |
347 |
|
T27 |
849 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13017167 |
1 |
|
|
T23 |
153 |
|
T24 |
247 |
|
T25 |
292 |
| auto[1] |
2769716 |
1 |
|
|
T24 |
82 |
|
T26 |
163 |
|
T27 |
246 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9002165 |
1 |
|
|
T23 |
153 |
|
T24 |
160 |
|
T25 |
292 |
| auto[1] |
6784718 |
1 |
|
|
T24 |
169 |
|
T26 |
318 |
|
T27 |
1023 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2010253 |
1 |
|
|
T24 |
55 |
|
T26 |
55 |
|
T27 |
447 |
| auto[1] |
auto[0] |
auto[1] |
1386770 |
1 |
|
|
T24 |
42 |
|
T26 |
59 |
|
T27 |
123 |
| auto[1] |
auto[1] |
auto[0] |
2004749 |
1 |
|
|
T24 |
32 |
|
T26 |
100 |
|
T27 |
330 |
| auto[1] |
auto[1] |
auto[1] |
1382946 |
1 |
|
|
T24 |
40 |
|
T26 |
104 |
|
T27 |
123 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |