Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8974733 |
1 |
|
|
T23 |
153 |
|
T24 |
176 |
|
T25 |
292 |
| auto[1] |
6812150 |
1 |
|
|
T24 |
153 |
|
T26 |
324 |
|
T27 |
687 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13011770 |
1 |
|
|
T23 |
153 |
|
T24 |
235 |
|
T25 |
292 |
| auto[1] |
2775113 |
1 |
|
|
T24 |
94 |
|
T26 |
178 |
|
T27 |
262 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8983245 |
1 |
|
|
T23 |
153 |
|
T24 |
117 |
|
T25 |
292 |
| auto[1] |
6803638 |
1 |
|
|
T24 |
212 |
|
T26 |
370 |
|
T27 |
1067 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2015156 |
1 |
|
|
T24 |
48 |
|
T26 |
60 |
|
T27 |
471 |
| auto[1] |
auto[0] |
auto[1] |
1390478 |
1 |
|
|
T24 |
53 |
|
T26 |
66 |
|
T27 |
213 |
| auto[1] |
auto[1] |
auto[0] |
2013369 |
1 |
|
|
T24 |
70 |
|
T26 |
132 |
|
T27 |
334 |
| auto[1] |
auto[1] |
auto[1] |
1384635 |
1 |
|
|
T24 |
41 |
|
T26 |
112 |
|
T27 |
49 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |