Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8969612 |
1 |
|
|
T23 |
153 |
|
T24 |
169 |
|
T25 |
292 |
| auto[1] |
6817271 |
1 |
|
|
T24 |
160 |
|
T26 |
463 |
|
T27 |
851 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13016297 |
1 |
|
|
T23 |
153 |
|
T24 |
247 |
|
T25 |
292 |
| auto[1] |
2770586 |
1 |
|
|
T24 |
82 |
|
T26 |
205 |
|
T27 |
194 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8992501 |
1 |
|
|
T23 |
153 |
|
T24 |
185 |
|
T25 |
292 |
| auto[1] |
6794382 |
1 |
|
|
T24 |
144 |
|
T26 |
435 |
|
T27 |
758 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2010977 |
1 |
|
|
T24 |
28 |
|
T26 |
87 |
|
T27 |
339 |
| auto[1] |
auto[0] |
auto[1] |
1384114 |
1 |
|
|
T24 |
45 |
|
T26 |
73 |
|
T27 |
124 |
| auto[1] |
auto[1] |
auto[0] |
2012819 |
1 |
|
|
T24 |
34 |
|
T26 |
143 |
|
T27 |
225 |
| auto[1] |
auto[1] |
auto[1] |
1386472 |
1 |
|
|
T24 |
37 |
|
T26 |
132 |
|
T27 |
70 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |