Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14900454 |
1 |
|
|
T23 |
153 |
|
T24 |
319 |
|
T25 |
292 |
| auto[1] |
886429 |
1 |
|
|
T24 |
10 |
|
T26 |
49 |
|
T27 |
32 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8894471 |
1 |
|
|
T23 |
153 |
|
T24 |
170 |
|
T25 |
292 |
| auto[1] |
6892412 |
1 |
|
|
T24 |
159 |
|
T26 |
206 |
|
T27 |
818 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2993138 |
1 |
|
|
T24 |
65 |
|
T26 |
78 |
|
T27 |
351 |
| auto[1] |
auto[0] |
auto[1] |
440971 |
1 |
|
|
T24 |
3 |
|
T26 |
24 |
|
T27 |
17 |
| auto[1] |
auto[1] |
auto[0] |
3012845 |
1 |
|
|
T24 |
84 |
|
T26 |
79 |
|
T27 |
435 |
| auto[1] |
auto[1] |
auto[1] |
445458 |
1 |
|
|
T24 |
7 |
|
T26 |
25 |
|
T27 |
15 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |