Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8973736 |
1 |
|
|
T23 |
153 |
|
T24 |
166 |
|
T25 |
292 |
| auto[1] |
6813147 |
1 |
|
|
T24 |
163 |
|
T26 |
443 |
|
T27 |
939 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13009422 |
1 |
|
|
T23 |
153 |
|
T24 |
232 |
|
T25 |
292 |
| auto[1] |
2777461 |
1 |
|
|
T24 |
97 |
|
T26 |
125 |
|
T27 |
301 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8984430 |
1 |
|
|
T23 |
153 |
|
T24 |
125 |
|
T25 |
292 |
| auto[1] |
6802453 |
1 |
|
|
T24 |
204 |
|
T26 |
278 |
|
T27 |
879 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2019107 |
1 |
|
|
T24 |
51 |
|
T26 |
54 |
|
T27 |
257 |
| auto[1] |
auto[0] |
auto[1] |
1389126 |
1 |
|
|
T24 |
50 |
|
T26 |
44 |
|
T27 |
143 |
| auto[1] |
auto[1] |
auto[0] |
2005885 |
1 |
|
|
T24 |
56 |
|
T26 |
99 |
|
T27 |
321 |
| auto[1] |
auto[1] |
auto[1] |
1388335 |
1 |
|
|
T24 |
47 |
|
T26 |
81 |
|
T27 |
158 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |