Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8957197 |
1 |
|
|
T23 |
153 |
|
T24 |
147 |
|
T25 |
292 |
| auto[1] |
6829686 |
1 |
|
|
T24 |
182 |
|
T26 |
432 |
|
T27 |
906 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13011608 |
1 |
|
|
T23 |
153 |
|
T24 |
245 |
|
T25 |
292 |
| auto[1] |
2775275 |
1 |
|
|
T24 |
84 |
|
T26 |
267 |
|
T27 |
261 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8975679 |
1 |
|
|
T23 |
153 |
|
T24 |
132 |
|
T25 |
292 |
| auto[1] |
6811204 |
1 |
|
|
T24 |
197 |
|
T26 |
465 |
|
T27 |
1014 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2020461 |
1 |
|
|
T24 |
64 |
|
T26 |
82 |
|
T27 |
377 |
| auto[1] |
auto[0] |
auto[1] |
1390160 |
1 |
|
|
T24 |
27 |
|
T26 |
100 |
|
T27 |
158 |
| auto[1] |
auto[1] |
auto[0] |
2015468 |
1 |
|
|
T24 |
49 |
|
T26 |
116 |
|
T27 |
376 |
| auto[1] |
auto[1] |
auto[1] |
1385115 |
1 |
|
|
T24 |
57 |
|
T26 |
167 |
|
T27 |
103 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |