Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8960419 |
1 |
|
|
T23 |
153 |
|
T24 |
114 |
|
T25 |
292 |
| auto[1] |
6826464 |
1 |
|
|
T24 |
215 |
|
T26 |
373 |
|
T27 |
987 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12999132 |
1 |
|
|
T23 |
153 |
|
T24 |
242 |
|
T25 |
292 |
| auto[1] |
2787751 |
1 |
|
|
T24 |
87 |
|
T26 |
165 |
|
T27 |
238 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8957372 |
1 |
|
|
T23 |
153 |
|
T24 |
170 |
|
T25 |
292 |
| auto[1] |
6829511 |
1 |
|
|
T24 |
159 |
|
T26 |
332 |
|
T27 |
1020 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1998773 |
1 |
|
|
T24 |
18 |
|
T26 |
63 |
|
T27 |
336 |
| auto[1] |
auto[0] |
auto[1] |
1389667 |
1 |
|
|
T24 |
21 |
|
T26 |
63 |
|
T27 |
112 |
| auto[1] |
auto[1] |
auto[0] |
2042987 |
1 |
|
|
T24 |
54 |
|
T26 |
104 |
|
T27 |
446 |
| auto[1] |
auto[1] |
auto[1] |
1398084 |
1 |
|
|
T24 |
66 |
|
T26 |
102 |
|
T27 |
126 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |