Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8961936 |
1 |
|
|
T23 |
153 |
|
T24 |
143 |
|
T25 |
292 |
| auto[1] |
6824947 |
1 |
|
|
T24 |
186 |
|
T26 |
519 |
|
T27 |
827 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12991497 |
1 |
|
|
T23 |
153 |
|
T24 |
200 |
|
T25 |
292 |
| auto[1] |
2795386 |
1 |
|
|
T24 |
129 |
|
T26 |
72 |
|
T27 |
175 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8918658 |
1 |
|
|
T23 |
153 |
|
T24 |
101 |
|
T25 |
292 |
| auto[1] |
6868225 |
1 |
|
|
T24 |
228 |
|
T26 |
163 |
|
T27 |
903 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2036779 |
1 |
|
|
T24 |
45 |
|
T26 |
31 |
|
T27 |
445 |
| auto[1] |
auto[0] |
auto[1] |
1397222 |
1 |
|
|
T24 |
61 |
|
T26 |
23 |
|
T27 |
87 |
| auto[1] |
auto[1] |
auto[0] |
2036060 |
1 |
|
|
T24 |
54 |
|
T26 |
60 |
|
T27 |
283 |
| auto[1] |
auto[1] |
auto[1] |
1398164 |
1 |
|
|
T24 |
68 |
|
T26 |
49 |
|
T27 |
88 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |