Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8991201 |
1 |
|
|
T23 |
153 |
|
T24 |
180 |
|
T25 |
292 |
| auto[1] |
6795682 |
1 |
|
|
T24 |
149 |
|
T26 |
217 |
|
T27 |
875 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13012826 |
1 |
|
|
T23 |
153 |
|
T24 |
251 |
|
T25 |
292 |
| auto[1] |
2774057 |
1 |
|
|
T24 |
78 |
|
T26 |
150 |
|
T27 |
199 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8979763 |
1 |
|
|
T23 |
153 |
|
T24 |
153 |
|
T25 |
292 |
| auto[1] |
6807120 |
1 |
|
|
T24 |
176 |
|
T26 |
291 |
|
T27 |
863 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2030718 |
1 |
|
|
T24 |
56 |
|
T26 |
92 |
|
T27 |
347 |
| auto[1] |
auto[0] |
auto[1] |
1394441 |
1 |
|
|
T24 |
62 |
|
T26 |
99 |
|
T27 |
91 |
| auto[1] |
auto[1] |
auto[0] |
2002345 |
1 |
|
|
T24 |
42 |
|
T26 |
49 |
|
T27 |
317 |
| auto[1] |
auto[1] |
auto[1] |
1379616 |
1 |
|
|
T24 |
16 |
|
T26 |
51 |
|
T27 |
108 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |