Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8964829 |
1 |
|
|
T23 |
153 |
|
T24 |
211 |
|
T25 |
292 |
| auto[1] |
6822054 |
1 |
|
|
T24 |
118 |
|
T26 |
439 |
|
T27 |
790 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13007369 |
1 |
|
|
T23 |
153 |
|
T24 |
263 |
|
T25 |
292 |
| auto[1] |
2779514 |
1 |
|
|
T24 |
66 |
|
T26 |
129 |
|
T27 |
162 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8961992 |
1 |
|
|
T23 |
153 |
|
T24 |
206 |
|
T25 |
292 |
| auto[1] |
6824891 |
1 |
|
|
T24 |
123 |
|
T26 |
274 |
|
T27 |
853 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2022013 |
1 |
|
|
T24 |
39 |
|
T26 |
45 |
|
T27 |
333 |
| auto[1] |
auto[0] |
auto[1] |
1388994 |
1 |
|
|
T24 |
35 |
|
T26 |
44 |
|
T27 |
93 |
| auto[1] |
auto[1] |
auto[0] |
2023364 |
1 |
|
|
T24 |
18 |
|
T26 |
100 |
|
T27 |
358 |
| auto[1] |
auto[1] |
auto[1] |
1390520 |
1 |
|
|
T24 |
31 |
|
T26 |
85 |
|
T27 |
69 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |