Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8980431 |
1 |
|
|
T23 |
153 |
|
T24 |
145 |
|
T25 |
292 |
| auto[1] |
6806452 |
1 |
|
|
T24 |
184 |
|
T26 |
348 |
|
T27 |
819 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13002886 |
1 |
|
|
T23 |
153 |
|
T24 |
248 |
|
T25 |
292 |
| auto[1] |
2783997 |
1 |
|
|
T24 |
81 |
|
T26 |
210 |
|
T27 |
194 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8956272 |
1 |
|
|
T23 |
153 |
|
T24 |
181 |
|
T25 |
292 |
| auto[1] |
6830611 |
1 |
|
|
T24 |
148 |
|
T26 |
421 |
|
T27 |
896 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2036977 |
1 |
|
|
T24 |
24 |
|
T26 |
114 |
|
T27 |
418 |
| auto[1] |
auto[0] |
auto[1] |
1395914 |
1 |
|
|
T24 |
42 |
|
T26 |
91 |
|
T27 |
105 |
| auto[1] |
auto[1] |
auto[0] |
2009637 |
1 |
|
|
T24 |
43 |
|
T26 |
97 |
|
T27 |
284 |
| auto[1] |
auto[1] |
auto[1] |
1388083 |
1 |
|
|
T24 |
39 |
|
T26 |
119 |
|
T27 |
89 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |