Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9010668 |
1 |
|
|
T23 |
153 |
|
T24 |
145 |
|
T25 |
292 |
| auto[1] |
6776215 |
1 |
|
|
T24 |
184 |
|
T26 |
353 |
|
T27 |
953 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13010803 |
1 |
|
|
T23 |
153 |
|
T24 |
263 |
|
T25 |
292 |
| auto[1] |
2776080 |
1 |
|
|
T24 |
66 |
|
T26 |
259 |
|
T27 |
207 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8972879 |
1 |
|
|
T23 |
153 |
|
T24 |
204 |
|
T25 |
292 |
| auto[1] |
6814004 |
1 |
|
|
T24 |
125 |
|
T26 |
469 |
|
T27 |
907 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2019546 |
1 |
|
|
T24 |
35 |
|
T26 |
93 |
|
T27 |
278 |
| auto[1] |
auto[0] |
auto[1] |
1388002 |
1 |
|
|
T24 |
17 |
|
T26 |
138 |
|
T27 |
105 |
| auto[1] |
auto[1] |
auto[0] |
2018378 |
1 |
|
|
T24 |
24 |
|
T26 |
117 |
|
T27 |
422 |
| auto[1] |
auto[1] |
auto[1] |
1388078 |
1 |
|
|
T24 |
49 |
|
T26 |
121 |
|
T27 |
102 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |