Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8957004 |
1 |
|
|
T23 |
153 |
|
T24 |
134 |
|
T25 |
292 |
| auto[1] |
6829879 |
1 |
|
|
T24 |
195 |
|
T26 |
340 |
|
T27 |
871 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13019781 |
1 |
|
|
T23 |
153 |
|
T24 |
265 |
|
T25 |
292 |
| auto[1] |
2767102 |
1 |
|
|
T24 |
64 |
|
T26 |
154 |
|
T27 |
177 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8991215 |
1 |
|
|
T23 |
153 |
|
T24 |
200 |
|
T25 |
292 |
| auto[1] |
6795668 |
1 |
|
|
T24 |
129 |
|
T26 |
296 |
|
T27 |
845 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2009566 |
1 |
|
|
T24 |
24 |
|
T26 |
64 |
|
T27 |
375 |
| auto[1] |
auto[0] |
auto[1] |
1377141 |
1 |
|
|
T24 |
27 |
|
T26 |
63 |
|
T27 |
131 |
| auto[1] |
auto[1] |
auto[0] |
2019000 |
1 |
|
|
T24 |
41 |
|
T26 |
78 |
|
T27 |
293 |
| auto[1] |
auto[1] |
auto[1] |
1389961 |
1 |
|
|
T24 |
37 |
|
T26 |
91 |
|
T27 |
46 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |