Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8981691 |
1 |
|
|
T23 |
153 |
|
T24 |
122 |
|
T25 |
292 |
| auto[1] |
6805192 |
1 |
|
|
T24 |
207 |
|
T26 |
341 |
|
T27 |
900 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14912590 |
1 |
|
|
T23 |
153 |
|
T24 |
318 |
|
T25 |
292 |
| auto[1] |
874293 |
1 |
|
|
T24 |
11 |
|
T26 |
105 |
|
T27 |
40 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8977640 |
1 |
|
|
T23 |
153 |
|
T24 |
165 |
|
T25 |
292 |
| auto[1] |
6809243 |
1 |
|
|
T24 |
164 |
|
T26 |
508 |
|
T27 |
907 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2956191 |
1 |
|
|
T24 |
49 |
|
T26 |
176 |
|
T27 |
457 |
| auto[1] |
auto[0] |
auto[1] |
435241 |
1 |
|
|
T24 |
3 |
|
T26 |
51 |
|
T27 |
23 |
| auto[1] |
auto[1] |
auto[0] |
2978759 |
1 |
|
|
T24 |
104 |
|
T26 |
227 |
|
T27 |
410 |
| auto[1] |
auto[1] |
auto[1] |
439052 |
1 |
|
|
T24 |
8 |
|
T26 |
54 |
|
T27 |
17 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |