Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8976482 |
1 |
|
|
T23 |
153 |
|
T24 |
169 |
|
T25 |
292 |
| auto[1] |
6810401 |
1 |
|
|
T24 |
160 |
|
T26 |
401 |
|
T27 |
720 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13015546 |
1 |
|
|
T23 |
153 |
|
T24 |
232 |
|
T25 |
292 |
| auto[1] |
2771337 |
1 |
|
|
T24 |
97 |
|
T26 |
223 |
|
T27 |
183 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8965388 |
1 |
|
|
T23 |
153 |
|
T24 |
136 |
|
T25 |
292 |
| auto[1] |
6821495 |
1 |
|
|
T24 |
193 |
|
T26 |
497 |
|
T27 |
765 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2020272 |
1 |
|
|
T24 |
60 |
|
T26 |
150 |
|
T27 |
340 |
| auto[1] |
auto[0] |
auto[1] |
1389607 |
1 |
|
|
T24 |
55 |
|
T26 |
117 |
|
T27 |
136 |
| auto[1] |
auto[1] |
auto[0] |
2029886 |
1 |
|
|
T24 |
36 |
|
T26 |
124 |
|
T27 |
242 |
| auto[1] |
auto[1] |
auto[1] |
1381730 |
1 |
|
|
T24 |
42 |
|
T26 |
106 |
|
T27 |
47 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |