Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8964366 |
1 |
|
|
T23 |
153 |
|
T24 |
202 |
|
T25 |
292 |
| auto[1] |
6822517 |
1 |
|
|
T24 |
127 |
|
T26 |
433 |
|
T27 |
919 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13022493 |
1 |
|
|
T23 |
153 |
|
T24 |
234 |
|
T25 |
292 |
| auto[1] |
2764390 |
1 |
|
|
T24 |
95 |
|
T26 |
222 |
|
T27 |
161 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8997575 |
1 |
|
|
T23 |
153 |
|
T24 |
135 |
|
T25 |
292 |
| auto[1] |
6789308 |
1 |
|
|
T24 |
194 |
|
T26 |
418 |
|
T27 |
894 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2018359 |
1 |
|
|
T24 |
62 |
|
T26 |
90 |
|
T27 |
348 |
| auto[1] |
auto[0] |
auto[1] |
1386630 |
1 |
|
|
T24 |
66 |
|
T26 |
98 |
|
T27 |
67 |
| auto[1] |
auto[1] |
auto[0] |
2006559 |
1 |
|
|
T24 |
37 |
|
T26 |
106 |
|
T27 |
385 |
| auto[1] |
auto[1] |
auto[1] |
1377760 |
1 |
|
|
T24 |
29 |
|
T26 |
124 |
|
T27 |
94 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |