Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8966753 |
1 |
|
|
T23 |
153 |
|
T24 |
186 |
|
T25 |
292 |
| auto[1] |
6820130 |
1 |
|
|
T24 |
143 |
|
T26 |
266 |
|
T27 |
741 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14912478 |
1 |
|
|
T23 |
153 |
|
T24 |
323 |
|
T25 |
292 |
| auto[1] |
874405 |
1 |
|
|
T24 |
6 |
|
T26 |
85 |
|
T27 |
40 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8971972 |
1 |
|
|
T23 |
153 |
|
T24 |
186 |
|
T25 |
292 |
| auto[1] |
6814911 |
1 |
|
|
T24 |
143 |
|
T26 |
390 |
|
T27 |
926 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2970579 |
1 |
|
|
T24 |
61 |
|
T26 |
189 |
|
T27 |
454 |
| auto[1] |
auto[0] |
auto[1] |
437740 |
1 |
|
|
T24 |
3 |
|
T26 |
54 |
|
T27 |
16 |
| auto[1] |
auto[1] |
auto[0] |
2969927 |
1 |
|
|
T24 |
76 |
|
T26 |
116 |
|
T27 |
432 |
| auto[1] |
auto[1] |
auto[1] |
436665 |
1 |
|
|
T24 |
3 |
|
T26 |
31 |
|
T27 |
24 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |