Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8977706 |
1 |
|
|
T23 |
153 |
|
T24 |
178 |
|
T25 |
292 |
| auto[1] |
6809177 |
1 |
|
|
T24 |
151 |
|
T26 |
170 |
|
T27 |
689 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14914763 |
1 |
|
|
T23 |
153 |
|
T24 |
314 |
|
T25 |
292 |
| auto[1] |
872120 |
1 |
|
|
T24 |
15 |
|
T26 |
76 |
|
T27 |
17 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8995171 |
1 |
|
|
T23 |
153 |
|
T24 |
179 |
|
T25 |
292 |
| auto[1] |
6791712 |
1 |
|
|
T24 |
150 |
|
T26 |
373 |
|
T27 |
638 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2971026 |
1 |
|
|
T24 |
82 |
|
T26 |
185 |
|
T27 |
415 |
| auto[1] |
auto[0] |
auto[1] |
438230 |
1 |
|
|
T24 |
10 |
|
T26 |
48 |
|
T27 |
12 |
| auto[1] |
auto[1] |
auto[0] |
2948566 |
1 |
|
|
T24 |
53 |
|
T26 |
112 |
|
T27 |
206 |
| auto[1] |
auto[1] |
auto[1] |
433890 |
1 |
|
|
T24 |
5 |
|
T26 |
28 |
|
T27 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |