Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8944931 |
1 |
|
|
T23 |
153 |
|
T24 |
146 |
|
T25 |
292 |
| auto[1] |
6841952 |
1 |
|
|
T24 |
183 |
|
T26 |
255 |
|
T27 |
958 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14910232 |
1 |
|
|
T23 |
153 |
|
T24 |
316 |
|
T25 |
292 |
| auto[1] |
876651 |
1 |
|
|
T24 |
13 |
|
T26 |
65 |
|
T27 |
35 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8958928 |
1 |
|
|
T23 |
153 |
|
T24 |
178 |
|
T25 |
292 |
| auto[1] |
6827955 |
1 |
|
|
T24 |
151 |
|
T26 |
354 |
|
T27 |
815 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2963145 |
1 |
|
|
T24 |
56 |
|
T26 |
162 |
|
T27 |
408 |
| auto[1] |
auto[0] |
auto[1] |
435919 |
1 |
|
|
T24 |
3 |
|
T26 |
38 |
|
T27 |
16 |
| auto[1] |
auto[1] |
auto[0] |
2988159 |
1 |
|
|
T24 |
82 |
|
T26 |
127 |
|
T27 |
372 |
| auto[1] |
auto[1] |
auto[1] |
440732 |
1 |
|
|
T24 |
10 |
|
T26 |
27 |
|
T27 |
19 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |