Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8968730 |
1 |
|
|
T23 |
153 |
|
T24 |
133 |
|
T25 |
292 |
| auto[1] |
6818153 |
1 |
|
|
T24 |
196 |
|
T26 |
392 |
|
T27 |
966 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14913078 |
1 |
|
|
T23 |
153 |
|
T24 |
321 |
|
T25 |
292 |
| auto[1] |
873805 |
1 |
|
|
T24 |
8 |
|
T26 |
67 |
|
T27 |
36 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8980023 |
1 |
|
|
T23 |
153 |
|
T24 |
191 |
|
T25 |
292 |
| auto[1] |
6806860 |
1 |
|
|
T24 |
138 |
|
T26 |
337 |
|
T27 |
951 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2967381 |
1 |
|
|
T24 |
65 |
|
T26 |
114 |
|
T27 |
419 |
| auto[1] |
auto[0] |
auto[1] |
437230 |
1 |
|
|
T24 |
3 |
|
T26 |
25 |
|
T27 |
14 |
| auto[1] |
auto[1] |
auto[0] |
2965674 |
1 |
|
|
T24 |
65 |
|
T26 |
156 |
|
T27 |
496 |
| auto[1] |
auto[1] |
auto[1] |
436575 |
1 |
|
|
T24 |
5 |
|
T26 |
42 |
|
T27 |
22 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |