Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8962778 |
1 |
|
|
T23 |
153 |
|
T24 |
230 |
|
T25 |
292 |
| auto[1] |
6824105 |
1 |
|
|
T24 |
99 |
|
T26 |
464 |
|
T27 |
998 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14905181 |
1 |
|
|
T23 |
153 |
|
T24 |
318 |
|
T25 |
292 |
| auto[1] |
881702 |
1 |
|
|
T24 |
11 |
|
T26 |
60 |
|
T27 |
27 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8925981 |
1 |
|
|
T23 |
153 |
|
T24 |
162 |
|
T25 |
292 |
| auto[1] |
6860902 |
1 |
|
|
T24 |
167 |
|
T26 |
321 |
|
T27 |
713 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2999770 |
1 |
|
|
T24 |
127 |
|
T26 |
97 |
|
T27 |
326 |
| auto[1] |
auto[0] |
auto[1] |
441911 |
1 |
|
|
T24 |
11 |
|
T26 |
21 |
|
T27 |
15 |
| auto[1] |
auto[1] |
auto[0] |
2979430 |
1 |
|
|
T24 |
29 |
|
T26 |
164 |
|
T27 |
360 |
| auto[1] |
auto[1] |
auto[1] |
439791 |
1 |
|
|
T26 |
39 |
|
T27 |
12 |
|
T32 |
3208 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |