Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8950501 |
1 |
|
|
T23 |
153 |
|
T24 |
214 |
|
T25 |
292 |
| auto[1] |
6836382 |
1 |
|
|
T24 |
115 |
|
T26 |
269 |
|
T27 |
946 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14909536 |
1 |
|
|
T23 |
153 |
|
T24 |
322 |
|
T25 |
292 |
| auto[1] |
877347 |
1 |
|
|
T24 |
7 |
|
T26 |
56 |
|
T27 |
34 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8963772 |
1 |
|
|
T23 |
153 |
|
T24 |
202 |
|
T25 |
292 |
| auto[1] |
6823111 |
1 |
|
|
T24 |
127 |
|
T26 |
270 |
|
T27 |
898 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2974053 |
1 |
|
|
T24 |
73 |
|
T26 |
126 |
|
T27 |
393 |
| auto[1] |
auto[0] |
auto[1] |
439463 |
1 |
|
|
T24 |
3 |
|
T26 |
31 |
|
T27 |
13 |
| auto[1] |
auto[1] |
auto[0] |
2971711 |
1 |
|
|
T24 |
47 |
|
T26 |
88 |
|
T27 |
471 |
| auto[1] |
auto[1] |
auto[1] |
437884 |
1 |
|
|
T24 |
4 |
|
T26 |
25 |
|
T27 |
21 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |