Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 946
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T104 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.112819512 May 30 01:00:30 PM PDT 24 May 30 01:00:32 PM PDT 24 32180421 ps
T765 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.3979148455 May 30 01:00:20 PM PDT 24 May 30 01:00:22 PM PDT 24 51823692 ps
T766 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3632184694 May 30 01:00:08 PM PDT 24 May 30 01:00:10 PM PDT 24 89397458 ps
T767 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.847798228 May 30 01:00:26 PM PDT 24 May 30 01:00:29 PM PDT 24 29757125 ps
T768 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1116639878 May 30 01:00:24 PM PDT 24 May 30 01:00:27 PM PDT 24 19282027 ps
T769 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1977924851 May 30 01:00:10 PM PDT 24 May 30 01:00:12 PM PDT 24 1187115857 ps
T91 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2602100169 May 30 01:00:36 PM PDT 24 May 30 01:00:38 PM PDT 24 48353207 ps
T770 /workspace/coverage/cover_reg_top/38.gpio_intr_test.4069057463 May 30 01:00:24 PM PDT 24 May 30 01:00:26 PM PDT 24 18805653 ps
T771 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2642566169 May 30 01:00:21 PM PDT 24 May 30 01:00:24 PM PDT 24 38441116 ps
T55 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.3205270354 May 30 01:00:30 PM PDT 24 May 30 01:00:32 PM PDT 24 105669589 ps
T772 /workspace/coverage/cover_reg_top/35.gpio_intr_test.1440967485 May 30 01:00:25 PM PDT 24 May 30 01:00:28 PM PDT 24 34440008 ps
T773 /workspace/coverage/cover_reg_top/29.gpio_intr_test.3081608994 May 30 01:00:26 PM PDT 24 May 30 01:00:28 PM PDT 24 43535676 ps
T774 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1389282999 May 30 01:00:24 PM PDT 24 May 30 01:00:27 PM PDT 24 41517917 ps
T48 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.940403399 May 30 01:00:26 PM PDT 24 May 30 01:00:29 PM PDT 24 96922517 ps
T775 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1097889300 May 30 01:00:17 PM PDT 24 May 30 01:00:19 PM PDT 24 234930226 ps
T776 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1548983206 May 30 01:00:22 PM PDT 24 May 30 01:00:27 PM PDT 24 413951755 ps
T777 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2253263826 May 30 01:00:02 PM PDT 24 May 30 01:00:03 PM PDT 24 36083661 ps
T778 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1868435942 May 30 01:00:22 PM PDT 24 May 30 01:00:24 PM PDT 24 15528763 ps
T779 /workspace/coverage/cover_reg_top/14.gpio_intr_test.4275368828 May 30 01:00:24 PM PDT 24 May 30 01:00:26 PM PDT 24 10859656 ps
T780 /workspace/coverage/cover_reg_top/39.gpio_intr_test.1148972933 May 30 01:00:25 PM PDT 24 May 30 01:00:28 PM PDT 24 35600750 ps
T49 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.4107392039 May 30 01:00:27 PM PDT 24 May 30 01:00:30 PM PDT 24 326358823 ps
T92 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.1980384551 May 30 01:00:26 PM PDT 24 May 30 01:00:28 PM PDT 24 13731794 ps
T781 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2273444950 May 30 01:00:13 PM PDT 24 May 30 01:00:14 PM PDT 24 77746344 ps
T782 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2834923335 May 30 01:00:23 PM PDT 24 May 30 01:00:26 PM PDT 24 17927546 ps
T783 /workspace/coverage/cover_reg_top/26.gpio_intr_test.2740210339 May 30 01:00:30 PM PDT 24 May 30 01:00:31 PM PDT 24 52755001 ps
T784 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.4261373620 May 30 01:00:27 PM PDT 24 May 30 01:00:29 PM PDT 24 42676027 ps
T785 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1297349113 May 30 01:00:20 PM PDT 24 May 30 01:00:21 PM PDT 24 15096341 ps
T786 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.415331866 May 30 01:00:19 PM PDT 24 May 30 01:00:21 PM PDT 24 38569712 ps
T787 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2558463117 May 30 01:00:21 PM PDT 24 May 30 01:00:23 PM PDT 24 66425224 ps
T788 /workspace/coverage/cover_reg_top/34.gpio_intr_test.2377525816 May 30 01:00:31 PM PDT 24 May 30 01:00:33 PM PDT 24 148357345 ps
T789 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1384062148 May 30 01:00:13 PM PDT 24 May 30 01:00:14 PM PDT 24 132941103 ps
T790 /workspace/coverage/cover_reg_top/45.gpio_intr_test.3054775409 May 30 01:00:26 PM PDT 24 May 30 01:00:28 PM PDT 24 56705645 ps
T791 /workspace/coverage/cover_reg_top/11.gpio_intr_test.3752331912 May 30 01:00:22 PM PDT 24 May 30 01:00:23 PM PDT 24 14192866 ps
T792 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.2651108377 May 30 01:00:02 PM PDT 24 May 30 01:00:03 PM PDT 24 606947444 ps
T793 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2598115920 May 30 01:00:22 PM PDT 24 May 30 01:00:25 PM PDT 24 314017710 ps
T794 /workspace/coverage/cover_reg_top/48.gpio_intr_test.157771876 May 30 01:00:31 PM PDT 24 May 30 01:00:33 PM PDT 24 14407983 ps
T795 /workspace/coverage/cover_reg_top/32.gpio_intr_test.205252631 May 30 01:00:22 PM PDT 24 May 30 01:00:25 PM PDT 24 47559046 ps
T796 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2042798203 May 30 01:00:30 PM PDT 24 May 30 01:00:32 PM PDT 24 74387128 ps
T797 /workspace/coverage/cover_reg_top/17.gpio_intr_test.1684367951 May 30 01:00:26 PM PDT 24 May 30 01:00:28 PM PDT 24 15081494 ps
T798 /workspace/coverage/cover_reg_top/21.gpio_intr_test.1689701868 May 30 01:00:22 PM PDT 24 May 30 01:00:24 PM PDT 24 27027142 ps
T799 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.4031792331 May 30 01:00:17 PM PDT 24 May 30 01:00:19 PM PDT 24 36182102 ps
T800 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.4106397056 May 30 01:00:18 PM PDT 24 May 30 01:00:20 PM PDT 24 73837052 ps
T51 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2048913828 May 30 01:00:44 PM PDT 24 May 30 01:00:45 PM PDT 24 267069630 ps
T801 /workspace/coverage/cover_reg_top/0.gpio_intr_test.2747483274 May 30 01:00:01 PM PDT 24 May 30 01:00:03 PM PDT 24 40496595 ps
T802 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.3514599418 May 30 01:00:02 PM PDT 24 May 30 01:00:06 PM PDT 24 1227558574 ps
T803 /workspace/coverage/cover_reg_top/49.gpio_intr_test.2835361190 May 30 01:00:26 PM PDT 24 May 30 01:00:28 PM PDT 24 41762819 ps
T804 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3261268602 May 30 01:00:23 PM PDT 24 May 30 01:00:26 PM PDT 24 15091722 ps
T93 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.653218173 May 30 01:00:14 PM PDT 24 May 30 01:00:16 PM PDT 24 33653666 ps
T805 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2193731847 May 30 01:00:19 PM PDT 24 May 30 01:00:22 PM PDT 24 24397177 ps
T806 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.72138413 May 30 01:00:21 PM PDT 24 May 30 01:00:23 PM PDT 24 47047114 ps
T807 /workspace/coverage/cover_reg_top/6.gpio_intr_test.1267362745 May 30 01:00:16 PM PDT 24 May 30 01:00:17 PM PDT 24 50253238 ps
T808 /workspace/coverage/cover_reg_top/3.gpio_intr_test.771346632 May 30 01:00:20 PM PDT 24 May 30 01:00:21 PM PDT 24 14663466 ps
T809 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2772561399 May 30 01:00:25 PM PDT 24 May 30 01:00:28 PM PDT 24 18982958 ps
T94 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1315972707 May 30 01:00:23 PM PDT 24 May 30 01:00:25 PM PDT 24 14105446 ps
T810 /workspace/coverage/cover_reg_top/28.gpio_intr_test.3302906774 May 30 01:00:31 PM PDT 24 May 30 01:00:33 PM PDT 24 13089137 ps
T95 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.822446566 May 30 01:00:23 PM PDT 24 May 30 01:00:26 PM PDT 24 14190044 ps
T811 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3996769557 May 30 01:00:24 PM PDT 24 May 30 01:00:32 PM PDT 24 132106156 ps
T812 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.3231778000 May 30 01:00:23 PM PDT 24 May 30 01:00:26 PM PDT 24 632753175 ps
T813 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2846042816 May 30 01:00:27 PM PDT 24 May 30 01:00:29 PM PDT 24 14933440 ps
T814 /workspace/coverage/cover_reg_top/4.gpio_intr_test.3846686516 May 30 01:00:19 PM PDT 24 May 30 01:00:21 PM PDT 24 53856580 ps
T815 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2805068317 May 30 01:00:23 PM PDT 24 May 30 01:00:25 PM PDT 24 16611797 ps
T816 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.235954734 May 30 01:00:07 PM PDT 24 May 30 01:00:09 PM PDT 24 12521084 ps
T817 /workspace/coverage/cover_reg_top/23.gpio_intr_test.2769915260 May 30 01:00:27 PM PDT 24 May 30 01:00:29 PM PDT 24 53965366 ps
T818 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.2925832466 May 30 01:00:14 PM PDT 24 May 30 01:00:15 PM PDT 24 18919740 ps
T819 /workspace/coverage/cover_reg_top/47.gpio_intr_test.1110340202 May 30 01:00:27 PM PDT 24 May 30 01:00:29 PM PDT 24 47411257 ps
T820 /workspace/coverage/cover_reg_top/9.gpio_intr_test.1069879619 May 30 01:00:27 PM PDT 24 May 30 01:00:29 PM PDT 24 14304700 ps
T821 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.747957875 May 30 01:00:25 PM PDT 24 May 30 01:00:28 PM PDT 24 17366893 ps
T96 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.3380203664 May 30 01:00:09 PM PDT 24 May 30 01:00:10 PM PDT 24 43206781 ps
T822 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1354205831 May 30 01:00:22 PM PDT 24 May 30 01:00:24 PM PDT 24 43039658 ps
T823 /workspace/coverage/cover_reg_top/20.gpio_intr_test.3923337580 May 30 01:00:23 PM PDT 24 May 30 01:00:25 PM PDT 24 35668819 ps
T824 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.4089567407 May 30 01:00:05 PM PDT 24 May 30 01:00:06 PM PDT 24 13484264 ps
T825 /workspace/coverage/cover_reg_top/8.gpio_intr_test.2213600963 May 30 01:00:21 PM PDT 24 May 30 01:00:22 PM PDT 24 11790278 ps
T826 /workspace/coverage/cover_reg_top/37.gpio_intr_test.3775315388 May 30 01:00:25 PM PDT 24 May 30 01:00:28 PM PDT 24 12841842 ps
T827 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.424809237 May 30 01:00:08 PM PDT 24 May 30 01:00:12 PM PDT 24 420898636 ps
T828 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.1703351288 May 30 01:00:22 PM PDT 24 May 30 01:00:25 PM PDT 24 79084783 ps
T829 /workspace/coverage/cover_reg_top/7.gpio_intr_test.2792446805 May 30 01:00:14 PM PDT 24 May 30 01:00:15 PM PDT 24 45101844 ps
T52 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3069840097 May 30 01:00:12 PM PDT 24 May 30 01:00:14 PM PDT 24 344494334 ps
T830 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.95000429 May 30 01:00:16 PM PDT 24 May 30 01:00:19 PM PDT 24 337317674 ps
T831 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.795813006 May 30 01:00:08 PM PDT 24 May 30 01:00:09 PM PDT 24 22753624 ps
T832 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.2092307042 May 30 01:00:15 PM PDT 24 May 30 01:00:17 PM PDT 24 146947988 ps
T833 /workspace/coverage/cover_reg_top/41.gpio_intr_test.2238895162 May 30 01:00:30 PM PDT 24 May 30 01:00:32 PM PDT 24 26678590 ps
T834 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3296036417 May 30 01:00:23 PM PDT 24 May 30 01:00:26 PM PDT 24 38530184 ps
T835 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.3103526613 May 30 01:00:15 PM PDT 24 May 30 01:00:17 PM PDT 24 40932713 ps
T836 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2803528238 May 30 01:00:18 PM PDT 24 May 30 01:00:20 PM PDT 24 112742448 ps
T837 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.546189405 May 30 01:00:23 PM PDT 24 May 30 01:00:25 PM PDT 24 40473568 ps
T838 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.3252937696 May 30 01:00:08 PM PDT 24 May 30 01:00:09 PM PDT 24 46590413 ps
T839 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.306216963 May 30 01:00:16 PM PDT 24 May 30 01:00:18 PM PDT 24 55738331 ps
T840 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2143974058 May 30 01:00:27 PM PDT 24 May 30 01:00:29 PM PDT 24 328919179 ps
T841 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.187664416 May 30 01:00:24 PM PDT 24 May 30 01:00:27 PM PDT 24 29749335 ps
T842 /workspace/coverage/cover_reg_top/46.gpio_intr_test.864125802 May 30 01:00:38 PM PDT 24 May 30 01:00:44 PM PDT 24 12667749 ps
T97 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.4068541559 May 30 01:00:19 PM PDT 24 May 30 01:00:21 PM PDT 24 18018360 ps
T843 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3400477634 May 30 01:00:27 PM PDT 24 May 30 01:00:30 PM PDT 24 156073476 ps
T844 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2896264141 May 30 01:00:22 PM PDT 24 May 30 01:00:25 PM PDT 24 304162167 ps
T845 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2617322833 May 30 01:00:07 PM PDT 24 May 30 01:00:09 PM PDT 24 41435842 ps
T846 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.201737080 May 30 01:00:22 PM PDT 24 May 30 01:00:26 PM PDT 24 1618535373 ps
T98 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.963043363 May 30 01:00:23 PM PDT 24 May 30 01:00:28 PM PDT 24 1544542087 ps
T847 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3244123084 May 30 01:15:53 PM PDT 24 May 30 01:15:56 PM PDT 24 80716751 ps
T848 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.780318943 May 30 01:15:47 PM PDT 24 May 30 01:15:49 PM PDT 24 47553791 ps
T849 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3057806057 May 30 01:16:06 PM PDT 24 May 30 01:16:10 PM PDT 24 330045323 ps
T850 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2715727846 May 30 01:15:46 PM PDT 24 May 30 01:15:48 PM PDT 24 239863449 ps
T851 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2168463136 May 30 01:16:05 PM PDT 24 May 30 01:16:08 PM PDT 24 270338928 ps
T852 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2656385884 May 30 01:15:31 PM PDT 24 May 30 01:15:33 PM PDT 24 37127473 ps
T853 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1169604579 May 30 01:15:57 PM PDT 24 May 30 01:15:59 PM PDT 24 427385070 ps
T854 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.4273468627 May 30 01:15:40 PM PDT 24 May 30 01:15:42 PM PDT 24 32623342 ps
T855 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1459892002 May 30 01:15:30 PM PDT 24 May 30 01:15:32 PM PDT 24 43014926 ps
T856 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2186986370 May 30 01:15:55 PM PDT 24 May 30 01:15:57 PM PDT 24 82264047 ps
T857 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3080620030 May 30 01:16:10 PM PDT 24 May 30 01:16:12 PM PDT 24 66582628 ps
T858 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3818014120 May 30 01:15:42 PM PDT 24 May 30 01:15:44 PM PDT 24 427861522 ps
T859 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2687250926 May 30 01:15:55 PM PDT 24 May 30 01:15:57 PM PDT 24 99030191 ps
T860 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2429711598 May 30 01:15:56 PM PDT 24 May 30 01:15:59 PM PDT 24 361191242 ps
T861 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3162362583 May 30 01:15:32 PM PDT 24 May 30 01:15:35 PM PDT 24 888182161 ps
T862 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2415015675 May 30 01:16:10 PM PDT 24 May 30 01:16:12 PM PDT 24 51791407 ps
T863 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3710443165 May 30 01:15:47 PM PDT 24 May 30 01:15:49 PM PDT 24 35483032 ps
T864 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1133527173 May 30 01:15:40 PM PDT 24 May 30 01:15:42 PM PDT 24 59863585 ps
T865 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.832589254 May 30 01:15:58 PM PDT 24 May 30 01:16:00 PM PDT 24 111863427 ps
T866 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2095552191 May 30 01:16:04 PM PDT 24 May 30 01:16:05 PM PDT 24 176905618 ps
T867 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3410622450 May 30 01:16:06 PM PDT 24 May 30 01:16:08 PM PDT 24 31795573 ps
T868 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1684179038 May 30 01:16:07 PM PDT 24 May 30 01:16:10 PM PDT 24 986511103 ps
T869 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1495306136 May 30 01:16:04 PM PDT 24 May 30 01:16:06 PM PDT 24 265789313 ps
T870 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2073535796 May 30 01:15:47 PM PDT 24 May 30 01:15:49 PM PDT 24 190298021 ps
T871 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3938709412 May 30 01:15:55 PM PDT 24 May 30 01:15:57 PM PDT 24 41435927 ps
T872 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3774902105 May 30 01:15:31 PM PDT 24 May 30 01:15:33 PM PDT 24 100094865 ps
T873 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1855762752 May 30 01:15:39 PM PDT 24 May 30 01:15:42 PM PDT 24 69415722 ps
T874 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2432069947 May 30 01:15:57 PM PDT 24 May 30 01:15:59 PM PDT 24 190486354 ps
T875 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3126343706 May 30 01:16:08 PM PDT 24 May 30 01:16:11 PM PDT 24 271573483 ps
T876 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1147342489 May 30 01:16:06 PM PDT 24 May 30 01:16:09 PM PDT 24 241880731 ps
T877 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2527861959 May 30 01:15:41 PM PDT 24 May 30 01:15:44 PM PDT 24 60499801 ps
T878 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1157748617 May 30 01:15:41 PM PDT 24 May 30 01:15:44 PM PDT 24 43696826 ps
T879 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.540653586 May 30 01:15:55 PM PDT 24 May 30 01:15:57 PM PDT 24 293623604 ps
T880 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3837706503 May 30 01:15:39 PM PDT 24 May 30 01:15:41 PM PDT 24 185391247 ps
T881 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2280640234 May 30 01:15:40 PM PDT 24 May 30 01:15:42 PM PDT 24 64871613 ps
T882 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2799491686 May 30 01:16:06 PM PDT 24 May 30 01:16:09 PM PDT 24 220809024 ps
T883 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2285467682 May 30 01:15:40 PM PDT 24 May 30 01:15:43 PM PDT 24 79226660 ps
T884 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.4124750904 May 30 01:15:56 PM PDT 24 May 30 01:15:58 PM PDT 24 37781913 ps
T885 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2963007262 May 30 01:15:55 PM PDT 24 May 30 01:15:57 PM PDT 24 53651460 ps
T886 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1991790210 May 30 01:16:08 PM PDT 24 May 30 01:16:11 PM PDT 24 265175174 ps
T887 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.983441509 May 30 01:15:47 PM PDT 24 May 30 01:15:49 PM PDT 24 918433115 ps
T888 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1689191736 May 30 01:15:42 PM PDT 24 May 30 01:15:45 PM PDT 24 191138960 ps
T889 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3935155108 May 30 01:15:45 PM PDT 24 May 30 01:15:48 PM PDT 24 82073132 ps
T890 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1487797212 May 30 01:15:56 PM PDT 24 May 30 01:15:59 PM PDT 24 72726786 ps
T891 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.579178109 May 30 01:15:40 PM PDT 24 May 30 01:15:43 PM PDT 24 130411236 ps
T892 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3464773226 May 30 01:15:57 PM PDT 24 May 30 01:15:59 PM PDT 24 69084912 ps
T893 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1443890055 May 30 01:16:09 PM PDT 24 May 30 01:16:12 PM PDT 24 44648933 ps
T894 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1122449495 May 30 01:16:07 PM PDT 24 May 30 01:16:10 PM PDT 24 113343801 ps
T895 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2496146493 May 30 01:16:05 PM PDT 24 May 30 01:16:07 PM PDT 24 434511664 ps
T896 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1123879243 May 30 01:15:57 PM PDT 24 May 30 01:15:59 PM PDT 24 88491586 ps
T897 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.162490839 May 30 01:15:31 PM PDT 24 May 30 01:15:33 PM PDT 24 88287403 ps
T898 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2105931995 May 30 01:15:57 PM PDT 24 May 30 01:15:59 PM PDT 24 101572283 ps
T899 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2620376057 May 30 01:15:33 PM PDT 24 May 30 01:15:35 PM PDT 24 569109944 ps
T900 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.996733137 May 30 01:15:30 PM PDT 24 May 30 01:15:33 PM PDT 24 74681556 ps
T901 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1260285016 May 30 01:16:04 PM PDT 24 May 30 01:16:06 PM PDT 24 58597373 ps
T902 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.394599590 May 30 01:15:40 PM PDT 24 May 30 01:15:43 PM PDT 24 218482840 ps
T903 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2669445659 May 30 01:15:57 PM PDT 24 May 30 01:15:59 PM PDT 24 61353733 ps
T904 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2435450666 May 30 01:15:41 PM PDT 24 May 30 01:15:43 PM PDT 24 405556790 ps
T905 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4107668652 May 30 01:16:08 PM PDT 24 May 30 01:16:11 PM PDT 24 125209109 ps
T906 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2032773621 May 30 01:15:55 PM PDT 24 May 30 01:15:56 PM PDT 24 160918624 ps
T907 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3657687583 May 30 01:16:05 PM PDT 24 May 30 01:16:07 PM PDT 24 243762601 ps
T908 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3879446809 May 30 01:16:06 PM PDT 24 May 30 01:16:09 PM PDT 24 50652022 ps
T909 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.271817110 May 30 01:15:32 PM PDT 24 May 30 01:15:34 PM PDT 24 445329879 ps
T910 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.513019195 May 30 01:15:56 PM PDT 24 May 30 01:15:59 PM PDT 24 106746444 ps
T911 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2731129939 May 30 01:16:05 PM PDT 24 May 30 01:16:08 PM PDT 24 194450329 ps
T912 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1702763172 May 30 01:15:29 PM PDT 24 May 30 01:15:32 PM PDT 24 172947147 ps
T913 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.127237633 May 30 01:15:43 PM PDT 24 May 30 01:15:46 PM PDT 24 56249198 ps
T914 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3698474996 May 30 01:15:45 PM PDT 24 May 30 01:15:48 PM PDT 24 46989185 ps
T915 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2044751194 May 30 01:15:40 PM PDT 24 May 30 01:15:43 PM PDT 24 155587811 ps
T916 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.177591921 May 30 01:15:45 PM PDT 24 May 30 01:15:48 PM PDT 24 189461861 ps
T917 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3070983665 May 30 01:16:04 PM PDT 24 May 30 01:16:07 PM PDT 24 40620457 ps
T918 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1175271028 May 30 01:15:57 PM PDT 24 May 30 01:15:59 PM PDT 24 91578942 ps
T919 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1844540070 May 30 01:15:57 PM PDT 24 May 30 01:15:59 PM PDT 24 37413395 ps
T920 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2420886129 May 30 01:15:54 PM PDT 24 May 30 01:15:56 PM PDT 24 57157905 ps
T921 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2952081470 May 30 01:15:54 PM PDT 24 May 30 01:15:56 PM PDT 24 43614501 ps
T922 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1086587440 May 30 01:15:47 PM PDT 24 May 30 01:15:49 PM PDT 24 36843301 ps
T923 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.4079000477 May 30 01:15:46 PM PDT 24 May 30 01:15:48 PM PDT 24 138836871 ps
T924 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3499913571 May 30 01:15:58 PM PDT 24 May 30 01:16:00 PM PDT 24 310172438 ps
T925 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3339181944 May 30 01:15:46 PM PDT 24 May 30 01:15:48 PM PDT 24 129078352 ps
T926 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3398480351 May 30 01:15:45 PM PDT 24 May 30 01:15:47 PM PDT 24 87690146 ps
T927 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.492627625 May 30 01:16:06 PM PDT 24 May 30 01:16:10 PM PDT 24 803064149 ps
T928 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1141848566 May 30 01:15:28 PM PDT 24 May 30 01:15:30 PM PDT 24 30432848 ps
T929 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3209284522 May 30 01:15:33 PM PDT 24 May 30 01:15:35 PM PDT 24 71149325 ps
T930 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1775947115 May 30 01:15:55 PM PDT 24 May 30 01:15:57 PM PDT 24 90815543 ps
T931 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1193689638 May 30 01:15:40 PM PDT 24 May 30 01:15:43 PM PDT 24 53426591 ps
T932 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3809664578 May 30 01:15:55 PM PDT 24 May 30 01:15:56 PM PDT 24 47710144 ps
T933 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1057301802 May 30 01:15:46 PM PDT 24 May 30 01:15:48 PM PDT 24 109944172 ps
T934 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3539043200 May 30 01:15:44 PM PDT 24 May 30 01:15:47 PM PDT 24 41792862 ps
T935 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2863102857 May 30 01:15:30 PM PDT 24 May 30 01:15:33 PM PDT 24 126506938 ps
T936 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.795935182 May 30 01:16:07 PM PDT 24 May 30 01:16:10 PM PDT 24 76302262 ps
T937 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.77570646 May 30 01:15:31 PM PDT 24 May 30 01:15:34 PM PDT 24 99030702 ps
T938 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.228415401 May 30 01:15:42 PM PDT 24 May 30 01:15:45 PM PDT 24 329164021 ps
T939 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2284771821 May 30 01:15:40 PM PDT 24 May 30 01:15:43 PM PDT 24 79384972 ps
T940 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3736771344 May 30 01:15:41 PM PDT 24 May 30 01:15:43 PM PDT 24 286637659 ps
T941 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3282184502 May 30 01:16:09 PM PDT 24 May 30 01:16:12 PM PDT 24 71876184 ps
T942 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2595272779 May 30 01:16:10 PM PDT 24 May 30 01:16:12 PM PDT 24 89255542 ps
T943 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.698045022 May 30 01:15:39 PM PDT 24 May 30 01:15:41 PM PDT 24 36317051 ps
T944 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1602988621 May 30 01:15:54 PM PDT 24 May 30 01:15:56 PM PDT 24 49814511 ps
T945 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1238608016 May 30 01:15:30 PM PDT 24 May 30 01:15:33 PM PDT 24 53797021 ps
T946 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1264174355 May 30 01:15:55 PM PDT 24 May 30 01:15:57 PM PDT 24 52460342 ps

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.3446191815
Short name T27
Test name
Test status
Simulation time 1231077998 ps
CPU time 5.28 seconds
Started May 30 02:30:47 PM PDT 24
Finished May 30 02:30:54 PM PDT 24
Peak memory 197784 kb
Host smart-1bca7b8c-e387-4bca-8d05-d5e18892d38a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446191815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.3446191815
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.3753487576
Short name T11
Test name
Test status
Simulation time 48971714 ps
CPU time 2.07 seconds
Started May 30 02:32:34 PM PDT 24
Finished May 30 02:32:38 PM PDT 24
Peak memory 198108 kb
Host smart-ba79b30d-b7d6-4a21-bc7e-354f668f204f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753487576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.3753487576
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.3642554907
Short name T36
Test name
Test status
Simulation time 417261202411 ps
CPU time 2073.47 seconds
Started May 30 02:31:45 PM PDT 24
Finished May 30 03:06:22 PM PDT 24
Peak memory 198244 kb
Host smart-ec2d905f-115c-49ab-a7e6-655419fd6441
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3642554907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.3642554907
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.3754679689
Short name T42
Test name
Test status
Simulation time 74335846 ps
CPU time 0.79 seconds
Started May 30 02:30:55 PM PDT 24
Finished May 30 02:30:57 PM PDT 24
Peak memory 214648 kb
Host smart-5101f89f-253b-4692-aaa7-239dedd8d600
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754679689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.3754679689
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2552516990
Short name T82
Test name
Test status
Simulation time 31703165 ps
CPU time 0.89 seconds
Started May 30 01:00:11 PM PDT 24
Finished May 30 01:00:12 PM PDT 24
Peak memory 197756 kb
Host smart-6da23b3a-c410-4989-819b-6496d2180fe9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552516990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.2552516990
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/default/13.gpio_stress_all.4123013041
Short name T1
Test name
Test status
Simulation time 56796385152 ps
CPU time 168.28 seconds
Started May 30 02:31:14 PM PDT 24
Finished May 30 02:34:04 PM PDT 24
Peak memory 198248 kb
Host smart-bb970c40-64ee-455c-9352-d349565b4224
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123013041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.4123013041
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.2862661157
Short name T40
Test name
Test status
Simulation time 126630188 ps
CPU time 1.39 seconds
Started May 30 01:00:21 PM PDT 24
Finished May 30 01:00:24 PM PDT 24
Peak memory 197880 kb
Host smart-e7d272da-e267-4130-a683-c04f0d844c6f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862661157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.2862661157
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/23.gpio_alert_test.3034966096
Short name T28
Test name
Test status
Simulation time 75460283 ps
CPU time 0.56 seconds
Started May 30 02:31:43 PM PDT 24
Finished May 30 02:31:45 PM PDT 24
Peak memory 193944 kb
Host smart-92d8617e-f654-4f74-a220-9dd6f82e493c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034966096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.3034966096
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.872168688
Short name T99
Test name
Test status
Simulation time 13344147 ps
CPU time 0.59 seconds
Started May 30 01:00:17 PM PDT 24
Finished May 30 01:00:19 PM PDT 24
Peak memory 194448 kb
Host smart-9b903ad2-e845-487f-b9bd-083df4c16aba
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872168688 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.gpio_same_csr_outstanding.872168688
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.3205270354
Short name T55
Test name
Test status
Simulation time 105669589 ps
CPU time 1.19 seconds
Started May 30 01:00:30 PM PDT 24
Finished May 30 01:00:32 PM PDT 24
Peak memory 197868 kb
Host smart-ae1acb3a-f878-48ef-8805-eda7daa5f55b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205270354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.3205270354
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2048913828
Short name T51
Test name
Test status
Simulation time 267069630 ps
CPU time 1.09 seconds
Started May 30 01:00:44 PM PDT 24
Finished May 30 01:00:45 PM PDT 24
Peak memory 197944 kb
Host smart-553f77ac-4a8b-459b-b570-a0e696676e41
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048913828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.2048913828
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.424809237
Short name T827
Test name
Test status
Simulation time 420898636 ps
CPU time 3.17 seconds
Started May 30 01:00:08 PM PDT 24
Finished May 30 01:00:12 PM PDT 24
Peak memory 197024 kb
Host smart-49c6ff82-8dee-42bf-8c46-1a112d1348f8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424809237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.424809237
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1721302620
Short name T89
Test name
Test status
Simulation time 35758085 ps
CPU time 0.66 seconds
Started May 30 01:00:07 PM PDT 24
Finished May 30 01:00:09 PM PDT 24
Peak memory 194288 kb
Host smart-5bc00476-00ac-48b2-b4fd-611f3bfe70e3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721302620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.1721302620
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2403729059
Short name T748
Test name
Test status
Simulation time 26224083 ps
CPU time 0.72 seconds
Started May 30 01:00:14 PM PDT 24
Finished May 30 01:00:15 PM PDT 24
Peak memory 197272 kb
Host smart-97fb431f-5bd7-4586-b066-8f17faa0876e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403729059 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.2403729059
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.235954734
Short name T816
Test name
Test status
Simulation time 12521084 ps
CPU time 0.58 seconds
Started May 30 01:00:07 PM PDT 24
Finished May 30 01:00:09 PM PDT 24
Peak memory 194604 kb
Host smart-f657c8a1-4ebb-4b78-a3d2-d9a80e144af6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235954734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_
csr_rw.235954734
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.2747483274
Short name T801
Test name
Test status
Simulation time 40496595 ps
CPU time 0.57 seconds
Started May 30 01:00:01 PM PDT 24
Finished May 30 01:00:03 PM PDT 24
Peak memory 194220 kb
Host smart-c7ca80dc-1dfb-418b-88d2-6f8ddd0a967a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747483274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.2747483274
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2273444950
Short name T781
Test name
Test status
Simulation time 77746344 ps
CPU time 0.78 seconds
Started May 30 01:00:13 PM PDT 24
Finished May 30 01:00:14 PM PDT 24
Peak memory 196036 kb
Host smart-4b14ec0d-d142-494a-8905-2bfe58a00a95
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273444950 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.2273444950
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.3103526613
Short name T835
Test name
Test status
Simulation time 40932713 ps
CPU time 1 seconds
Started May 30 01:00:15 PM PDT 24
Finished May 30 01:00:17 PM PDT 24
Peak memory 197872 kb
Host smart-cbc3536b-e19b-4488-9e64-4d675282589d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103526613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.3103526613
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.2651108377
Short name T792
Test name
Test status
Simulation time 606947444 ps
CPU time 0.91 seconds
Started May 30 01:00:02 PM PDT 24
Finished May 30 01:00:03 PM PDT 24
Peak memory 197700 kb
Host smart-6cf2ef0f-ad83-4f63-b58f-6c39202604e2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651108377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.2651108377
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2382567717
Short name T749
Test name
Test status
Simulation time 23927780 ps
CPU time 0.66 seconds
Started May 30 01:00:06 PM PDT 24
Finished May 30 01:00:07 PM PDT 24
Peak memory 193976 kb
Host smart-04b1e494-e21e-4336-94b7-b501bd86e779
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382567717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.2382567717
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.3514599418
Short name T802
Test name
Test status
Simulation time 1227558574 ps
CPU time 3.25 seconds
Started May 30 01:00:02 PM PDT 24
Finished May 30 01:00:06 PM PDT 24
Peak memory 197784 kb
Host smart-5009579b-63e7-466e-b44c-a7152716a5b2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514599418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.3514599418
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.3380203664
Short name T96
Test name
Test status
Simulation time 43206781 ps
CPU time 0.63 seconds
Started May 30 01:00:09 PM PDT 24
Finished May 30 01:00:10 PM PDT 24
Peak memory 194596 kb
Host smart-305b85b5-ca89-4ba7-8181-687dd3eb3b28
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380203664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.3380203664
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.4031792331
Short name T799
Test name
Test status
Simulation time 36182102 ps
CPU time 1.09 seconds
Started May 30 01:00:17 PM PDT 24
Finished May 30 01:00:19 PM PDT 24
Peak memory 197892 kb
Host smart-e5fee371-7de4-483e-b1b3-ebab5a62cbd9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031792331 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.4031792331
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.3252937696
Short name T838
Test name
Test status
Simulation time 46590413 ps
CPU time 0.7 seconds
Started May 30 01:00:08 PM PDT 24
Finished May 30 01:00:09 PM PDT 24
Peak memory 194676 kb
Host smart-e9239c88-f837-43df-b5a3-682573c272d2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252937696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.3252937696
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.1785549192
Short name T732
Test name
Test status
Simulation time 45712833 ps
CPU time 0.6 seconds
Started May 30 01:00:17 PM PDT 24
Finished May 30 01:00:18 PM PDT 24
Peak memory 193632 kb
Host smart-9f139680-32f1-4261-99f0-4a4b4bbfe72d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785549192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.1785549192
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.95000429
Short name T830
Test name
Test status
Simulation time 337317674 ps
CPU time 2.91 seconds
Started May 30 01:00:16 PM PDT 24
Finished May 30 01:00:19 PM PDT 24
Peak memory 197896 kb
Host smart-2040800b-506f-4ac3-8a7e-d601f03c6966
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95000429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.95000429
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.1837497896
Short name T721
Test name
Test status
Simulation time 93298004 ps
CPU time 0.79 seconds
Started May 30 01:00:23 PM PDT 24
Finished May 30 01:00:26 PM PDT 24
Peak memory 197852 kb
Host smart-e41ef1f3-cc03-4f5f-9501-5e3c81b2a45f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837497896 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.1837497896
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.4293249418
Short name T86
Test name
Test status
Simulation time 21639395 ps
CPU time 0.54 seconds
Started May 30 01:00:11 PM PDT 24
Finished May 30 01:00:12 PM PDT 24
Peak memory 193844 kb
Host smart-359a816d-b433-4967-83b6-63ec542d8b1d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293249418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.4293249418
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.419099244
Short name T747
Test name
Test status
Simulation time 14016389 ps
CPU time 0.58 seconds
Started May 30 01:00:17 PM PDT 24
Finished May 30 01:00:18 PM PDT 24
Peak memory 193592 kb
Host smart-5699a910-f119-444f-9f6a-722a29786b5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419099244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.419099244
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.2925832466
Short name T818
Test name
Test status
Simulation time 18919740 ps
CPU time 0.79 seconds
Started May 30 01:00:14 PM PDT 24
Finished May 30 01:00:15 PM PDT 24
Peak memory 196200 kb
Host smart-85f010af-0ca5-480c-b964-b30dd27255bd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925832466 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.2925832466
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2642566169
Short name T771
Test name
Test status
Simulation time 38441116 ps
CPU time 1.87 seconds
Started May 30 01:00:21 PM PDT 24
Finished May 30 01:00:24 PM PDT 24
Peak memory 197924 kb
Host smart-fd6b5c08-9cd9-48bf-8c43-02951b610e5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642566169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.2642566169
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1097889300
Short name T775
Test name
Test status
Simulation time 234930226 ps
CPU time 1.35 seconds
Started May 30 01:00:17 PM PDT 24
Finished May 30 01:00:19 PM PDT 24
Peak memory 197920 kb
Host smart-98a4dcff-a9d6-4ea5-9800-4d7a9c4e43d7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097889300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1097889300
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2193731847
Short name T805
Test name
Test status
Simulation time 24397177 ps
CPU time 1.17 seconds
Started May 30 01:00:19 PM PDT 24
Finished May 30 01:00:22 PM PDT 24
Peak memory 198052 kb
Host smart-e1f549b6-7424-4fbf-9e5c-9c9193ae22fb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193731847 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.2193731847
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1389282999
Short name T774
Test name
Test status
Simulation time 41517917 ps
CPU time 0.67 seconds
Started May 30 01:00:24 PM PDT 24
Finished May 30 01:00:27 PM PDT 24
Peak memory 195012 kb
Host smart-2f196600-e316-47ff-a12b-11f43ed8e87b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389282999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.1389282999
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.3752331912
Short name T791
Test name
Test status
Simulation time 14192866 ps
CPU time 0.61 seconds
Started May 30 01:00:22 PM PDT 24
Finished May 30 01:00:23 PM PDT 24
Peak memory 193572 kb
Host smart-c407b699-6d07-4342-9966-e32b4456d3b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752331912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.3752331912
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3261268602
Short name T804
Test name
Test status
Simulation time 15091722 ps
CPU time 0.68 seconds
Started May 30 01:00:23 PM PDT 24
Finished May 30 01:00:26 PM PDT 24
Peak memory 195616 kb
Host smart-5e0157f0-cd17-4285-9cfc-e6731615d6f2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261268602 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.3261268602
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2896264141
Short name T844
Test name
Test status
Simulation time 304162167 ps
CPU time 0.94 seconds
Started May 30 01:00:22 PM PDT 24
Finished May 30 01:00:25 PM PDT 24
Peak memory 197828 kb
Host smart-462377c1-a9a0-4efe-80cd-c6908dcd8421
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896264141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.2896264141
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.546189405
Short name T837
Test name
Test status
Simulation time 40473568 ps
CPU time 0.89 seconds
Started May 30 01:00:23 PM PDT 24
Finished May 30 01:00:25 PM PDT 24
Peak memory 197160 kb
Host smart-6c841de0-21e7-4fc2-855a-ee6fe576a01e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546189405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.gpio_tl_intg_err.546189405
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2834923335
Short name T782
Test name
Test status
Simulation time 17927546 ps
CPU time 0.66 seconds
Started May 30 01:00:23 PM PDT 24
Finished May 30 01:00:26 PM PDT 24
Peak memory 196612 kb
Host smart-916c86d4-6748-4ffd-91d4-80e71a6b40f4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834923335 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.2834923335
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1354205831
Short name T822
Test name
Test status
Simulation time 43039658 ps
CPU time 0.59 seconds
Started May 30 01:00:22 PM PDT 24
Finished May 30 01:00:24 PM PDT 24
Peak memory 194504 kb
Host smart-f0a3b86c-f88d-477f-b0f2-479bc88a0686
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354205831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.1354205831
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.3367457518
Short name T731
Test name
Test status
Simulation time 12818753 ps
CPU time 0.62 seconds
Started May 30 01:00:24 PM PDT 24
Finished May 30 01:00:27 PM PDT 24
Peak memory 194208 kb
Host smart-b6183565-942f-44a6-af41-825ea9b4b996
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367457518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.3367457518
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.550493822
Short name T100
Test name
Test status
Simulation time 35925624 ps
CPU time 0.85 seconds
Started May 30 01:00:25 PM PDT 24
Finished May 30 01:00:28 PM PDT 24
Peak memory 197036 kb
Host smart-c5ac18dc-e153-4244-ac59-5c102a4b00d0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550493822 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 12.gpio_same_csr_outstanding.550493822
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3400477634
Short name T843
Test name
Test status
Simulation time 156073476 ps
CPU time 1.98 seconds
Started May 30 01:00:27 PM PDT 24
Finished May 30 01:00:30 PM PDT 24
Peak memory 197988 kb
Host smart-f45bc157-41d1-4d87-8a90-0a2819058914
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400477634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.3400477634
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1445351933
Short name T53
Test name
Test status
Simulation time 819050613 ps
CPU time 1.46 seconds
Started May 30 01:00:23 PM PDT 24
Finished May 30 01:00:26 PM PDT 24
Peak memory 197956 kb
Host smart-46c54432-0e73-4095-9d1f-45ce910df689
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445351933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.1445351933
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.3979148455
Short name T765
Test name
Test status
Simulation time 51823692 ps
CPU time 0.68 seconds
Started May 30 01:00:20 PM PDT 24
Finished May 30 01:00:22 PM PDT 24
Peak memory 196916 kb
Host smart-3d597c44-ad5b-4e33-8007-c724003216b4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979148455 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.3979148455
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.1008317218
Short name T763
Test name
Test status
Simulation time 11894816 ps
CPU time 0.56 seconds
Started May 30 01:00:22 PM PDT 24
Finished May 30 01:00:24 PM PDT 24
Peak memory 194532 kb
Host smart-62f5f0f0-5569-4c2a-9990-d4ca7356bc9a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008317218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.1008317218
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.152279434
Short name T735
Test name
Test status
Simulation time 42815959 ps
CPU time 0.58 seconds
Started May 30 01:00:24 PM PDT 24
Finished May 30 01:00:26 PM PDT 24
Peak memory 194212 kb
Host smart-27217021-fc9f-4c34-b321-5c878230eb00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152279434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.152279434
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1656366885
Short name T88
Test name
Test status
Simulation time 51859363 ps
CPU time 0.62 seconds
Started May 30 01:00:23 PM PDT 24
Finished May 30 01:00:25 PM PDT 24
Peak memory 195144 kb
Host smart-e387a3a1-bc41-472d-b23f-8526f24478a6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656366885 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.1656366885
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1392817517
Short name T753
Test name
Test status
Simulation time 60767988 ps
CPU time 1.41 seconds
Started May 30 01:00:22 PM PDT 24
Finished May 30 01:00:24 PM PDT 24
Peak memory 197952 kb
Host smart-a866faf9-3be9-4f31-9aba-687b20215dd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392817517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.1392817517
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2143974058
Short name T840
Test name
Test status
Simulation time 328919179 ps
CPU time 1.33 seconds
Started May 30 01:00:27 PM PDT 24
Finished May 30 01:00:29 PM PDT 24
Peak memory 197960 kb
Host smart-e63e4251-1c5b-4d69-b177-b279fcf35fc8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143974058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.2143974058
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1092221381
Short name T743
Test name
Test status
Simulation time 64986458 ps
CPU time 0.68 seconds
Started May 30 01:00:24 PM PDT 24
Finished May 30 01:00:26 PM PDT 24
Peak memory 196916 kb
Host smart-306ea0d0-8e38-42ba-9843-0900c6cc0b84
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092221381 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.1092221381
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3296036417
Short name T834
Test name
Test status
Simulation time 38530184 ps
CPU time 0.56 seconds
Started May 30 01:00:23 PM PDT 24
Finished May 30 01:00:26 PM PDT 24
Peak memory 193208 kb
Host smart-ef6dfe8f-b9bc-46ce-a2be-3a5a62501c95
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296036417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.3296036417
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.4275368828
Short name T779
Test name
Test status
Simulation time 10859656 ps
CPU time 0.56 seconds
Started May 30 01:00:24 PM PDT 24
Finished May 30 01:00:26 PM PDT 24
Peak memory 193420 kb
Host smart-2c8e15aa-ddd3-4b77-abed-dffb3e50f33d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275368828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.4275368828
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2846042816
Short name T813
Test name
Test status
Simulation time 14933440 ps
CPU time 0.65 seconds
Started May 30 01:00:27 PM PDT 24
Finished May 30 01:00:29 PM PDT 24
Peak memory 194644 kb
Host smart-61ef2b60-993a-4d39-8993-582fdc806b36
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846042816 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.2846042816
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.3296947679
Short name T750
Test name
Test status
Simulation time 643375267 ps
CPU time 3.17 seconds
Started May 30 01:00:20 PM PDT 24
Finished May 30 01:00:24 PM PDT 24
Peak memory 197924 kb
Host smart-e331146e-6e08-4aa3-a8d2-efc6fce7f4de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296947679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.3296947679
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1868435942
Short name T778
Test name
Test status
Simulation time 15528763 ps
CPU time 0.66 seconds
Started May 30 01:00:22 PM PDT 24
Finished May 30 01:00:24 PM PDT 24
Peak memory 196260 kb
Host smart-8bf803d6-58e1-4e2e-9062-19694f4b30e6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868435942 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.1868435942
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2560179123
Short name T752
Test name
Test status
Simulation time 33162785 ps
CPU time 0.6 seconds
Started May 30 01:00:22 PM PDT 24
Finished May 30 01:00:24 PM PDT 24
Peak memory 194772 kb
Host smart-4af64e3f-c51e-4fa6-adf3-3f2e18d3c88a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560179123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.2560179123
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.1135253420
Short name T758
Test name
Test status
Simulation time 65957071 ps
CPU time 0.57 seconds
Started May 30 01:00:24 PM PDT 24
Finished May 30 01:00:26 PM PDT 24
Peak memory 194148 kb
Host smart-ce175b7a-e5d9-4f38-9024-505abbe243ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135253420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.1135253420
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1116639878
Short name T768
Test name
Test status
Simulation time 19282027 ps
CPU time 0.83 seconds
Started May 30 01:00:24 PM PDT 24
Finished May 30 01:00:27 PM PDT 24
Peak memory 196940 kb
Host smart-ed8e161f-d2aa-4ad4-9764-49227149565b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116639878 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.1116639878
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1548983206
Short name T776
Test name
Test status
Simulation time 413951755 ps
CPU time 3.44 seconds
Started May 30 01:00:22 PM PDT 24
Finished May 30 01:00:27 PM PDT 24
Peak memory 197932 kb
Host smart-2e0ed923-79e0-404f-a376-f92c5840caa6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548983206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.1548983206
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2772561399
Short name T809
Test name
Test status
Simulation time 18982958 ps
CPU time 0.93 seconds
Started May 30 01:00:25 PM PDT 24
Finished May 30 01:00:28 PM PDT 24
Peak memory 197828 kb
Host smart-11270735-58eb-4ec9-96f6-2700c8bedde3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772561399 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.2772561399
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1998493677
Short name T83
Test name
Test status
Simulation time 52922800 ps
CPU time 0.62 seconds
Started May 30 01:00:23 PM PDT 24
Finished May 30 01:00:25 PM PDT 24
Peak memory 194788 kb
Host smart-89e5cce9-df75-449e-bc31-6a631565d129
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998493677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.1998493677
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.3504443165
Short name T729
Test name
Test status
Simulation time 23526755 ps
CPU time 0.56 seconds
Started May 30 01:00:27 PM PDT 24
Finished May 30 01:00:29 PM PDT 24
Peak memory 194244 kb
Host smart-41afa546-eff5-417a-a682-5cbd3f8b59b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504443165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.3504443165
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1650404886
Short name T101
Test name
Test status
Simulation time 183177496 ps
CPU time 0.63 seconds
Started May 30 01:00:24 PM PDT 24
Finished May 30 01:00:27 PM PDT 24
Peak memory 195328 kb
Host smart-696ac04a-dab1-401d-8040-c7bee940b00c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650404886 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.1650404886
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1338549853
Short name T730
Test name
Test status
Simulation time 338058771 ps
CPU time 1.15 seconds
Started May 30 01:00:42 PM PDT 24
Finished May 30 01:00:43 PM PDT 24
Peak memory 197936 kb
Host smart-47aef870-2c92-43ad-9e91-4c09f04fbeb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338549853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1338549853
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.940403399
Short name T48
Test name
Test status
Simulation time 96922517 ps
CPU time 1.17 seconds
Started May 30 01:00:26 PM PDT 24
Finished May 30 01:00:29 PM PDT 24
Peak memory 197876 kb
Host smart-641600cd-97f0-4a22-aba8-9bbfdc583acf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940403399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.gpio_tl_intg_err.940403399
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.1703351288
Short name T828
Test name
Test status
Simulation time 79084783 ps
CPU time 0.89 seconds
Started May 30 01:00:22 PM PDT 24
Finished May 30 01:00:25 PM PDT 24
Peak memory 197916 kb
Host smart-2b40d003-b997-4171-b0a8-8d4ecddb0d58
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703351288 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.1703351288
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.1980384551
Short name T92
Test name
Test status
Simulation time 13731794 ps
CPU time 0.63 seconds
Started May 30 01:00:26 PM PDT 24
Finished May 30 01:00:28 PM PDT 24
Peak memory 195488 kb
Host smart-fac31d6e-fd31-431d-ab82-620a2e1eda85
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980384551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.1980384551
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.1684367951
Short name T797
Test name
Test status
Simulation time 15081494 ps
CPU time 0.59 seconds
Started May 30 01:00:26 PM PDT 24
Finished May 30 01:00:28 PM PDT 24
Peak memory 194212 kb
Host smart-a77a8910-a906-4f30-a435-591cd5089408
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684367951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.1684367951
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.112819512
Short name T104
Test name
Test status
Simulation time 32180421 ps
CPU time 0.78 seconds
Started May 30 01:00:30 PM PDT 24
Finished May 30 01:00:32 PM PDT 24
Peak memory 196932 kb
Host smart-dababdaf-b772-4a3f-b8e6-4b705b28226f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112819512 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 17.gpio_same_csr_outstanding.112819512
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.847798228
Short name T767
Test name
Test status
Simulation time 29757125 ps
CPU time 1.47 seconds
Started May 30 01:00:26 PM PDT 24
Finished May 30 01:00:29 PM PDT 24
Peak memory 197948 kb
Host smart-952538d2-b21e-436b-90a6-4cedcef0ebe4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847798228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.847798228
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1416701859
Short name T41
Test name
Test status
Simulation time 407360735 ps
CPU time 1.44 seconds
Started May 30 01:00:36 PM PDT 24
Finished May 30 01:00:38 PM PDT 24
Peak memory 197876 kb
Host smart-212cb8f1-5855-41c7-9195-0e50afde92d8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416701859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.1416701859
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.72138413
Short name T806
Test name
Test status
Simulation time 47047114 ps
CPU time 0.71 seconds
Started May 30 01:00:21 PM PDT 24
Finished May 30 01:00:23 PM PDT 24
Peak memory 197292 kb
Host smart-07931bf8-bfc2-4434-a7b1-a07b5acb6cc4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72138413 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.72138413
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.461965388
Short name T116
Test name
Test status
Simulation time 69015467 ps
CPU time 0.57 seconds
Started May 30 01:00:22 PM PDT 24
Finished May 30 01:00:24 PM PDT 24
Peak memory 193836 kb
Host smart-d929acd2-28be-4a6d-8e92-5222fc4cf49c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461965388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio
_csr_rw.461965388
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.3215950806
Short name T762
Test name
Test status
Simulation time 17006450 ps
CPU time 0.59 seconds
Started May 30 01:00:28 PM PDT 24
Finished May 30 01:00:30 PM PDT 24
Peak memory 193612 kb
Host smart-845ddea9-32d8-4560-9dab-a1b961be15fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215950806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.3215950806
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2042798203
Short name T796
Test name
Test status
Simulation time 74387128 ps
CPU time 0.68 seconds
Started May 30 01:00:30 PM PDT 24
Finished May 30 01:00:32 PM PDT 24
Peak memory 195348 kb
Host smart-71acfeaf-4eb0-493a-80ba-450ceaa78074
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042798203 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.2042798203
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3803778451
Short name T726
Test name
Test status
Simulation time 28525715 ps
CPU time 1.31 seconds
Started May 30 01:00:30 PM PDT 24
Finished May 30 01:00:32 PM PDT 24
Peak memory 197952 kb
Host smart-2c9340d3-2642-4c5c-8ac7-9f1e3802ea5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803778451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3803778451
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.3231778000
Short name T812
Test name
Test status
Simulation time 632753175 ps
CPU time 1.37 seconds
Started May 30 01:00:23 PM PDT 24
Finished May 30 01:00:26 PM PDT 24
Peak memory 197932 kb
Host smart-78f00767-0826-4e5f-b11f-6f71c58d92ce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231778000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.3231778000
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2878982661
Short name T724
Test name
Test status
Simulation time 178237458 ps
CPU time 1.04 seconds
Started May 30 01:00:41 PM PDT 24
Finished May 30 01:00:42 PM PDT 24
Peak memory 197908 kb
Host smart-dceb4394-0e43-4f18-9e54-d70b6eb8f95d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878982661 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.2878982661
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1502705840
Short name T80
Test name
Test status
Simulation time 39551049 ps
CPU time 0.62 seconds
Started May 30 01:00:25 PM PDT 24
Finished May 30 01:00:27 PM PDT 24
Peak memory 194800 kb
Host smart-50f93574-3d14-46fd-8c8a-7e083bba6e75
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502705840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.1502705840
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1543499178
Short name T734
Test name
Test status
Simulation time 17255997 ps
CPU time 0.62 seconds
Started May 30 01:00:24 PM PDT 24
Finished May 30 01:00:26 PM PDT 24
Peak memory 194220 kb
Host smart-3e512aa7-a7cb-4f66-ab16-2c7fcbe73e17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543499178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1543499178
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3996769557
Short name T811
Test name
Test status
Simulation time 132106156 ps
CPU time 0.89 seconds
Started May 30 01:00:24 PM PDT 24
Finished May 30 01:00:32 PM PDT 24
Peak memory 197124 kb
Host smart-0d8c1bf0-dc26-453f-85d6-d9e18aa19187
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996769557 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.3996769557
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1091239678
Short name T741
Test name
Test status
Simulation time 117213029 ps
CPU time 1.45 seconds
Started May 30 01:00:25 PM PDT 24
Finished May 30 01:00:28 PM PDT 24
Peak memory 197840 kb
Host smart-c6d1e38a-9f2f-4df5-8e57-dd4c9cd2cdbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091239678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.1091239678
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.4107392039
Short name T49
Test name
Test status
Simulation time 326358823 ps
CPU time 1.14 seconds
Started May 30 01:00:27 PM PDT 24
Finished May 30 01:00:30 PM PDT 24
Peak memory 197828 kb
Host smart-3173a187-c0af-4aed-8673-23848e5de5fd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107392039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.4107392039
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.653218173
Short name T93
Test name
Test status
Simulation time 33653666 ps
CPU time 0.84 seconds
Started May 30 01:00:14 PM PDT 24
Finished May 30 01:00:16 PM PDT 24
Peak memory 197760 kb
Host smart-5bf96a52-cee9-448f-814e-4a011111be9a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653218173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.gpio_csr_aliasing.653218173
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3347689297
Short name T81
Test name
Test status
Simulation time 397328035 ps
CPU time 2.26 seconds
Started May 30 01:00:10 PM PDT 24
Finished May 30 01:00:13 PM PDT 24
Peak memory 197924 kb
Host smart-61b75eb1-ffaa-4aa8-ad2a-ee29299f35fe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347689297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.3347689297
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.822446566
Short name T95
Test name
Test status
Simulation time 14190044 ps
CPU time 0.64 seconds
Started May 30 01:00:23 PM PDT 24
Finished May 30 01:00:26 PM PDT 24
Peak memory 194544 kb
Host smart-c817c003-c605-4bed-9e87-9c5b29015025
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822446566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.822446566
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1384062148
Short name T789
Test name
Test status
Simulation time 132941103 ps
CPU time 0.92 seconds
Started May 30 01:00:13 PM PDT 24
Finished May 30 01:00:14 PM PDT 24
Peak memory 197952 kb
Host smart-e78422a9-279f-45a3-8e55-22042c21a1e2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384062148 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.1384062148
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2253263826
Short name T777
Test name
Test status
Simulation time 36083661 ps
CPU time 0.58 seconds
Started May 30 01:00:02 PM PDT 24
Finished May 30 01:00:03 PM PDT 24
Peak memory 193196 kb
Host smart-da959eb2-e532-42bd-bc82-ae78d1ed4318
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253263826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.2253263826
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.1819470065
Short name T745
Test name
Test status
Simulation time 72402389 ps
CPU time 0.57 seconds
Started May 30 01:00:16 PM PDT 24
Finished May 30 01:00:17 PM PDT 24
Peak memory 194228 kb
Host smart-c366733e-86c2-4aea-a099-2ad5070da56b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819470065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.1819470065
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2617322833
Short name T845
Test name
Test status
Simulation time 41435842 ps
CPU time 0.65 seconds
Started May 30 01:00:07 PM PDT 24
Finished May 30 01:00:09 PM PDT 24
Peak memory 194816 kb
Host smart-992a7241-610a-4c13-8616-48a4d7c63331
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617322833 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.2617322833
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.4095393599
Short name T757
Test name
Test status
Simulation time 86367635 ps
CPU time 1.65 seconds
Started May 30 01:00:16 PM PDT 24
Finished May 30 01:00:18 PM PDT 24
Peak memory 197936 kb
Host smart-c57ed910-b87e-41b4-af42-91ddb9cdda6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095393599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.4095393599
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3069840097
Short name T52
Test name
Test status
Simulation time 344494334 ps
CPU time 1.12 seconds
Started May 30 01:00:12 PM PDT 24
Finished May 30 01:00:14 PM PDT 24
Peak memory 197928 kb
Host smart-18262519-6492-4309-a0f7-19a5ee2016cd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069840097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.3069840097
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.3923337580
Short name T823
Test name
Test status
Simulation time 35668819 ps
CPU time 0.56 seconds
Started May 30 01:00:23 PM PDT 24
Finished May 30 01:00:25 PM PDT 24
Peak memory 194180 kb
Host smart-023a346c-5ce4-4784-8789-a25c032b5ec9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923337580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.3923337580
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.1689701868
Short name T798
Test name
Test status
Simulation time 27027142 ps
CPU time 0.62 seconds
Started May 30 01:00:22 PM PDT 24
Finished May 30 01:00:24 PM PDT 24
Peak memory 193496 kb
Host smart-37cf7a6f-1547-4ce9-a3f0-b8ca563001f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689701868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.1689701868
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.1924596998
Short name T727
Test name
Test status
Simulation time 15307301 ps
CPU time 0.63 seconds
Started May 30 01:00:24 PM PDT 24
Finished May 30 01:00:26 PM PDT 24
Peak memory 194340 kb
Host smart-64056034-6c2c-45b7-8d5d-5e802e0a11a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924596998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.1924596998
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.2769915260
Short name T817
Test name
Test status
Simulation time 53965366 ps
CPU time 0.63 seconds
Started May 30 01:00:27 PM PDT 24
Finished May 30 01:00:29 PM PDT 24
Peak memory 194176 kb
Host smart-eac271d9-cf74-4e8d-9972-efabf9ab5618
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769915260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.2769915260
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.3714567286
Short name T764
Test name
Test status
Simulation time 36808600 ps
CPU time 0.65 seconds
Started May 30 01:00:31 PM PDT 24
Finished May 30 01:00:32 PM PDT 24
Peak memory 194328 kb
Host smart-f4d3cabe-3643-4d1d-b116-103ff5318727
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714567286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.3714567286
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.3572225210
Short name T746
Test name
Test status
Simulation time 14658223 ps
CPU time 0.61 seconds
Started May 30 01:00:22 PM PDT 24
Finished May 30 01:00:24 PM PDT 24
Peak memory 193612 kb
Host smart-3663c231-6baf-4359-a8fc-b51ce56de309
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572225210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.3572225210
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.2740210339
Short name T783
Test name
Test status
Simulation time 52755001 ps
CPU time 0.6 seconds
Started May 30 01:00:30 PM PDT 24
Finished May 30 01:00:31 PM PDT 24
Peak memory 193676 kb
Host smart-f140f6ba-1086-46a4-ab72-488bf06c3da6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740210339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.2740210339
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.1997340789
Short name T740
Test name
Test status
Simulation time 37355096 ps
CPU time 0.6 seconds
Started May 30 01:00:23 PM PDT 24
Finished May 30 01:00:25 PM PDT 24
Peak memory 193596 kb
Host smart-6161d65e-e156-44f7-b24a-a4af8a7e58ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997340789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.1997340789
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.3302906774
Short name T810
Test name
Test status
Simulation time 13089137 ps
CPU time 0.59 seconds
Started May 30 01:00:31 PM PDT 24
Finished May 30 01:00:33 PM PDT 24
Peak memory 194208 kb
Host smart-79a17a9c-c4e2-47d8-9239-ac4e4435fdb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302906774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.3302906774
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.3081608994
Short name T773
Test name
Test status
Simulation time 43535676 ps
CPU time 0.6 seconds
Started May 30 01:00:26 PM PDT 24
Finished May 30 01:00:28 PM PDT 24
Peak memory 193676 kb
Host smart-9be0a05a-f86a-49ae-94b2-6795a4ce40fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081608994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.3081608994
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.4068541559
Short name T97
Test name
Test status
Simulation time 18018360 ps
CPU time 0.85 seconds
Started May 30 01:00:19 PM PDT 24
Finished May 30 01:00:21 PM PDT 24
Peak memory 196620 kb
Host smart-14456aab-c8b6-459d-be03-4cca9aa25c7f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068541559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.4068541559
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.447614612
Short name T737
Test name
Test status
Simulation time 291444873 ps
CPU time 1.45 seconds
Started May 30 01:00:25 PM PDT 24
Finished May 30 01:00:28 PM PDT 24
Peak memory 197828 kb
Host smart-1120016a-0b42-448b-a61e-36ad0638251f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447614612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.447614612
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.4036948477
Short name T90
Test name
Test status
Simulation time 35792342 ps
CPU time 0.66 seconds
Started May 30 01:00:19 PM PDT 24
Finished May 30 01:00:21 PM PDT 24
Peak memory 194536 kb
Host smart-5355387d-398a-4981-9858-9c6aea26839d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036948477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.4036948477
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2860517388
Short name T744
Test name
Test status
Simulation time 23642237 ps
CPU time 0.77 seconds
Started May 30 01:00:27 PM PDT 24
Finished May 30 01:00:29 PM PDT 24
Peak memory 197856 kb
Host smart-cf4cade4-e4ff-4b5f-8a3a-46fb6fd5dfbf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860517388 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.2860517388
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.650749209
Short name T115
Test name
Test status
Simulation time 21320391 ps
CPU time 0.58 seconds
Started May 30 01:00:25 PM PDT 24
Finished May 30 01:00:27 PM PDT 24
Peak memory 193124 kb
Host smart-2f63f04f-d74c-45c2-877e-0f8b1444d00a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650749209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_
csr_rw.650749209
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.771346632
Short name T808
Test name
Test status
Simulation time 14663466 ps
CPU time 0.58 seconds
Started May 30 01:00:20 PM PDT 24
Finished May 30 01:00:21 PM PDT 24
Peak memory 193552 kb
Host smart-d9ce41fc-b8be-4a50-be83-3fcd72277e8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771346632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.771346632
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.425092965
Short name T103
Test name
Test status
Simulation time 16216212 ps
CPU time 0.67 seconds
Started May 30 01:00:21 PM PDT 24
Finished May 30 01:00:23 PM PDT 24
Peak memory 194708 kb
Host smart-6beb5ffb-5aaa-4614-83d1-42ae6df4244e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425092965 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.gpio_same_csr_outstanding.425092965
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.1453873875
Short name T720
Test name
Test status
Simulation time 405272934 ps
CPU time 1.34 seconds
Started May 30 01:00:09 PM PDT 24
Finished May 30 01:00:12 PM PDT 24
Peak memory 197968 kb
Host smart-dcfe438a-f3bb-4bd1-ae51-c8e50934216a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453873875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.1453873875
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.4106397056
Short name T800
Test name
Test status
Simulation time 73837052 ps
CPU time 1.13 seconds
Started May 30 01:00:18 PM PDT 24
Finished May 30 01:00:20 PM PDT 24
Peak memory 197896 kb
Host smart-b568dd07-515e-4ca8-b973-22082c1379e4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106397056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.4106397056
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.959093613
Short name T739
Test name
Test status
Simulation time 37366671 ps
CPU time 0.6 seconds
Started May 30 01:00:28 PM PDT 24
Finished May 30 01:00:30 PM PDT 24
Peak memory 194268 kb
Host smart-7623b669-3153-4546-9aa3-16b5c248c8ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959093613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.959093613
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.712885323
Short name T756
Test name
Test status
Simulation time 77284305 ps
CPU time 0.61 seconds
Started May 30 01:00:28 PM PDT 24
Finished May 30 01:00:30 PM PDT 24
Peak memory 194284 kb
Host smart-9c90e332-6520-4a9c-9d19-6cb802d8fb17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712885323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.712885323
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.205252631
Short name T795
Test name
Test status
Simulation time 47559046 ps
CPU time 0.6 seconds
Started May 30 01:00:22 PM PDT 24
Finished May 30 01:00:25 PM PDT 24
Peak memory 193660 kb
Host smart-d3245599-125c-4c1f-94af-276648258288
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205252631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.205252631
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.119211980
Short name T760
Test name
Test status
Simulation time 39287134 ps
CPU time 0.56 seconds
Started May 30 01:00:29 PM PDT 24
Finished May 30 01:00:31 PM PDT 24
Peak memory 193568 kb
Host smart-81b7b06a-22f2-4547-93a7-83e1bb2a123e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119211980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.119211980
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.2377525816
Short name T788
Test name
Test status
Simulation time 148357345 ps
CPU time 0.59 seconds
Started May 30 01:00:31 PM PDT 24
Finished May 30 01:00:33 PM PDT 24
Peak memory 193572 kb
Host smart-8cd71c23-ab70-4af1-b5fe-a3c5817bcfe6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377525816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.2377525816
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.1440967485
Short name T772
Test name
Test status
Simulation time 34440008 ps
CPU time 0.64 seconds
Started May 30 01:00:25 PM PDT 24
Finished May 30 01:00:28 PM PDT 24
Peak memory 193568 kb
Host smart-46998653-0930-4894-8e73-fae8b74b1eff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440967485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.1440967485
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.2152729397
Short name T754
Test name
Test status
Simulation time 55967938 ps
CPU time 0.61 seconds
Started May 30 01:00:31 PM PDT 24
Finished May 30 01:00:33 PM PDT 24
Peak memory 193604 kb
Host smart-052cf60a-34dc-4680-b5d3-ffcddf2bfb78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152729397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.2152729397
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.3775315388
Short name T826
Test name
Test status
Simulation time 12841842 ps
CPU time 0.6 seconds
Started May 30 01:00:25 PM PDT 24
Finished May 30 01:00:28 PM PDT 24
Peak memory 193660 kb
Host smart-9d0593ae-ac2d-4349-9476-0c0f369ebb3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775315388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.3775315388
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.4069057463
Short name T770
Test name
Test status
Simulation time 18805653 ps
CPU time 0.67 seconds
Started May 30 01:00:24 PM PDT 24
Finished May 30 01:00:26 PM PDT 24
Peak memory 194272 kb
Host smart-d6f5de20-6ca0-403b-99cf-eeeb290faf60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069057463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.4069057463
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.1148972933
Short name T780
Test name
Test status
Simulation time 35600750 ps
CPU time 0.63 seconds
Started May 30 01:00:25 PM PDT 24
Finished May 30 01:00:28 PM PDT 24
Peak memory 193624 kb
Host smart-9afb7091-f88a-4178-87b7-c92d4cf6774d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148972933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.1148972933
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2558463117
Short name T787
Test name
Test status
Simulation time 66425224 ps
CPU time 0.88 seconds
Started May 30 01:00:21 PM PDT 24
Finished May 30 01:00:23 PM PDT 24
Peak memory 197764 kb
Host smart-fd1e5e1e-8be6-496a-8596-b523d002d444
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558463117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.2558463117
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.963043363
Short name T98
Test name
Test status
Simulation time 1544542087 ps
CPU time 3.44 seconds
Started May 30 01:00:23 PM PDT 24
Finished May 30 01:00:28 PM PDT 24
Peak memory 196900 kb
Host smart-caf19e7c-8c90-47d0-8d5f-3c8d67661f8f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963043363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.963043363
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2602100169
Short name T91
Test name
Test status
Simulation time 48353207 ps
CPU time 0.68 seconds
Started May 30 01:00:36 PM PDT 24
Finished May 30 01:00:38 PM PDT 24
Peak memory 194880 kb
Host smart-67cfde1b-c0f4-4527-88d9-109dd9263b9f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602100169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.2602100169
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1723044238
Short name T736
Test name
Test status
Simulation time 34027100 ps
CPU time 0.9 seconds
Started May 30 01:00:09 PM PDT 24
Finished May 30 01:00:11 PM PDT 24
Peak memory 197904 kb
Host smart-d0d2b65b-72b1-43ba-8858-c92a7e2b50f7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723044238 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.1723044238
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1297349113
Short name T785
Test name
Test status
Simulation time 15096341 ps
CPU time 0.61 seconds
Started May 30 01:00:20 PM PDT 24
Finished May 30 01:00:21 PM PDT 24
Peak memory 194512 kb
Host smart-a4355591-f3de-4315-bb07-a79060a78566
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297349113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.1297349113
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.3846686516
Short name T814
Test name
Test status
Simulation time 53856580 ps
CPU time 0.62 seconds
Started May 30 01:00:19 PM PDT 24
Finished May 30 01:00:21 PM PDT 24
Peak memory 193652 kb
Host smart-31fad5c6-0c04-4492-96b8-09af9852217c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846686516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.3846686516
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1057559698
Short name T84
Test name
Test status
Simulation time 27739410 ps
CPU time 0.65 seconds
Started May 30 01:00:18 PM PDT 24
Finished May 30 01:00:19 PM PDT 24
Peak memory 194812 kb
Host smart-0e5ce2d7-c7a7-4a9e-bb11-53579fd15780
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057559698 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.1057559698
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1719659229
Short name T755
Test name
Test status
Simulation time 653771618 ps
CPU time 2.64 seconds
Started May 30 01:00:18 PM PDT 24
Finished May 30 01:00:22 PM PDT 24
Peak memory 197936 kb
Host smart-4ca0e426-9fa7-42c2-83d7-8a9dfcef55be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719659229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.1719659229
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.619906741
Short name T54
Test name
Test status
Simulation time 284522486 ps
CPU time 1.16 seconds
Started May 30 01:00:20 PM PDT 24
Finished May 30 01:00:22 PM PDT 24
Peak memory 197992 kb
Host smart-47f71da2-116b-477e-9df8-c3e97bf10436
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619906741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.gpio_tl_intg_err.619906741
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.1229809864
Short name T722
Test name
Test status
Simulation time 13674722 ps
CPU time 0.59 seconds
Started May 30 01:00:25 PM PDT 24
Finished May 30 01:00:28 PM PDT 24
Peak memory 193572 kb
Host smart-ebeea06b-1c37-4771-92ad-ec44b8d7fdf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229809864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.1229809864
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.2238895162
Short name T833
Test name
Test status
Simulation time 26678590 ps
CPU time 0.57 seconds
Started May 30 01:00:30 PM PDT 24
Finished May 30 01:00:32 PM PDT 24
Peak memory 194168 kb
Host smart-c4175926-1f2f-49b1-91f4-63c3a41933bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238895162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.2238895162
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.2583756034
Short name T733
Test name
Test status
Simulation time 24569834 ps
CPU time 0.6 seconds
Started May 30 01:00:34 PM PDT 24
Finished May 30 01:00:36 PM PDT 24
Peak memory 193600 kb
Host smart-2166aad9-e4dc-4d6e-9b0b-2126f5973399
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583756034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.2583756034
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.3733291608
Short name T725
Test name
Test status
Simulation time 20349727 ps
CPU time 0.56 seconds
Started May 30 01:00:28 PM PDT 24
Finished May 30 01:00:30 PM PDT 24
Peak memory 194184 kb
Host smart-f37d6178-b48c-4fdf-ab06-a4e6bef99fad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733291608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.3733291608
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.86551802
Short name T761
Test name
Test status
Simulation time 32698279 ps
CPU time 0.66 seconds
Started May 30 01:00:29 PM PDT 24
Finished May 30 01:00:31 PM PDT 24
Peak memory 193640 kb
Host smart-fc6d327f-3f18-44f5-ab6e-daee80fe5c08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86551802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.86551802
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.3054775409
Short name T790
Test name
Test status
Simulation time 56705645 ps
CPU time 0.61 seconds
Started May 30 01:00:26 PM PDT 24
Finished May 30 01:00:28 PM PDT 24
Peak memory 193600 kb
Host smart-9d2b02e4-b8fa-4dcd-9d6d-86d2332d1a6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054775409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.3054775409
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.864125802
Short name T842
Test name
Test status
Simulation time 12667749 ps
CPU time 0.58 seconds
Started May 30 01:00:38 PM PDT 24
Finished May 30 01:00:44 PM PDT 24
Peak memory 193556 kb
Host smart-2e9d9ab9-15f3-4127-9aa1-38cd93c1f6b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864125802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.864125802
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.1110340202
Short name T819
Test name
Test status
Simulation time 47411257 ps
CPU time 0.57 seconds
Started May 30 01:00:27 PM PDT 24
Finished May 30 01:00:29 PM PDT 24
Peak memory 193572 kb
Host smart-1afe32ee-c2f6-4a24-92c0-10cb06fb3d50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110340202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.1110340202
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.157771876
Short name T794
Test name
Test status
Simulation time 14407983 ps
CPU time 0.6 seconds
Started May 30 01:00:31 PM PDT 24
Finished May 30 01:00:33 PM PDT 24
Peak memory 193620 kb
Host smart-f98b7c5b-a399-4937-918d-e057b22a993d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157771876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.157771876
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.2835361190
Short name T803
Test name
Test status
Simulation time 41762819 ps
CPU time 0.58 seconds
Started May 30 01:00:26 PM PDT 24
Finished May 30 01:00:28 PM PDT 24
Peak memory 193628 kb
Host smart-67656eee-a674-4a21-942e-7399b551710b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835361190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.2835361190
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1891812071
Short name T742
Test name
Test status
Simulation time 284116532 ps
CPU time 0.95 seconds
Started May 30 01:00:23 PM PDT 24
Finished May 30 01:00:26 PM PDT 24
Peak memory 197928 kb
Host smart-bae31974-d503-4f1b-ab71-3941aa68e38c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891812071 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.1891812071
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1315972707
Short name T94
Test name
Test status
Simulation time 14105446 ps
CPU time 0.58 seconds
Started May 30 01:00:23 PM PDT 24
Finished May 30 01:00:25 PM PDT 24
Peak memory 193556 kb
Host smart-6f202862-90df-46e0-a684-853d703c5256
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315972707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.1315972707
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.2082275583
Short name T728
Test name
Test status
Simulation time 17284219 ps
CPU time 0.61 seconds
Started May 30 01:00:24 PM PDT 24
Finished May 30 01:00:26 PM PDT 24
Peak memory 193616 kb
Host smart-8245c51c-cdba-4e0e-97cb-0f9dd8468369
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082275583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.2082275583
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.666103635
Short name T102
Test name
Test status
Simulation time 56289012 ps
CPU time 0.83 seconds
Started May 30 01:00:15 PM PDT 24
Finished May 30 01:00:16 PM PDT 24
Peak memory 196284 kb
Host smart-71a09d36-aa0d-48d5-92d9-ba5897099c20
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666103635 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 5.gpio_same_csr_outstanding.666103635
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.393695789
Short name T759
Test name
Test status
Simulation time 84530113 ps
CPU time 2.43 seconds
Started May 30 01:00:20 PM PDT 24
Finished May 30 01:00:23 PM PDT 24
Peak memory 198012 kb
Host smart-ee24ba90-6985-433f-afc3-26175e23f35c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393695789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.393695789
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3502596045
Short name T50
Test name
Test status
Simulation time 418377424 ps
CPU time 1.5 seconds
Started May 30 01:00:23 PM PDT 24
Finished May 30 01:00:26 PM PDT 24
Peak memory 197952 kb
Host smart-8272262e-0c1d-4926-9d40-f9cfe8addd28
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502596045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.3502596045
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2803528238
Short name T836
Test name
Test status
Simulation time 112742448 ps
CPU time 1.4 seconds
Started May 30 01:00:18 PM PDT 24
Finished May 30 01:00:20 PM PDT 24
Peak memory 197960 kb
Host smart-0437c462-9f79-46a4-bb51-ac6f5a7087a5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803528238 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.2803528238
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.555187732
Short name T751
Test name
Test status
Simulation time 15758594 ps
CPU time 0.61 seconds
Started May 30 01:00:20 PM PDT 24
Finished May 30 01:00:21 PM PDT 24
Peak memory 195488 kb
Host smart-e510439b-845d-4a13-b189-bce18e04c1f2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555187732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_
csr_rw.555187732
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.1267362745
Short name T807
Test name
Test status
Simulation time 50253238 ps
CPU time 0.6 seconds
Started May 30 01:00:16 PM PDT 24
Finished May 30 01:00:17 PM PDT 24
Peak memory 194352 kb
Host smart-f31b6b8c-f638-405c-ab83-7a398b8c013a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267362745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.1267362745
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.747957875
Short name T821
Test name
Test status
Simulation time 17366893 ps
CPU time 1 seconds
Started May 30 01:00:25 PM PDT 24
Finished May 30 01:00:28 PM PDT 24
Peak memory 195776 kb
Host smart-fb809f1a-d544-44e2-bb7d-51537eccc95e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747957875 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 6.gpio_same_csr_outstanding.747957875
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.3916737846
Short name T723
Test name
Test status
Simulation time 89005468 ps
CPU time 1.35 seconds
Started May 30 01:00:26 PM PDT 24
Finished May 30 01:00:29 PM PDT 24
Peak memory 197944 kb
Host smart-e23874b5-bf7c-4a0c-a1eb-bd17545a8ee5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916737846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.3916737846
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2598115920
Short name T793
Test name
Test status
Simulation time 314017710 ps
CPU time 1.15 seconds
Started May 30 01:00:22 PM PDT 24
Finished May 30 01:00:25 PM PDT 24
Peak memory 197920 kb
Host smart-b099e065-9aee-4055-b48a-7a85ec14a127
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598115920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.2598115920
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.4261373620
Short name T784
Test name
Test status
Simulation time 42676027 ps
CPU time 0.75 seconds
Started May 30 01:00:27 PM PDT 24
Finished May 30 01:00:29 PM PDT 24
Peak memory 197692 kb
Host smart-5cd9f5b3-2af1-4868-b7c1-1f0f99e65259
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261373620 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.4261373620
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.4089567407
Short name T824
Test name
Test status
Simulation time 13484264 ps
CPU time 0.58 seconds
Started May 30 01:00:05 PM PDT 24
Finished May 30 01:00:06 PM PDT 24
Peak memory 194460 kb
Host smart-7905246e-3c06-4b20-88ed-a5faf3f7b1ab
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089567407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.4089567407
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.2792446805
Short name T829
Test name
Test status
Simulation time 45101844 ps
CPU time 0.62 seconds
Started May 30 01:00:14 PM PDT 24
Finished May 30 01:00:15 PM PDT 24
Peak memory 193588 kb
Host smart-366f3b21-d34b-4dbe-af2d-c5801716014a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792446805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.2792446805
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.711203865
Short name T87
Test name
Test status
Simulation time 337347273 ps
CPU time 0.81 seconds
Started May 30 01:00:24 PM PDT 24
Finished May 30 01:00:27 PM PDT 24
Peak memory 196884 kb
Host smart-d6960baf-737c-4cc9-bc85-4dbc14fa2a7d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711203865 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 7.gpio_same_csr_outstanding.711203865
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3632184694
Short name T766
Test name
Test status
Simulation time 89397458 ps
CPU time 1.67 seconds
Started May 30 01:00:08 PM PDT 24
Finished May 30 01:00:10 PM PDT 24
Peak memory 197964 kb
Host smart-c140b8e1-0999-4b78-951d-957f28c54761
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632184694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.3632184694
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1977924851
Short name T769
Test name
Test status
Simulation time 1187115857 ps
CPU time 1.35 seconds
Started May 30 01:00:10 PM PDT 24
Finished May 30 01:00:12 PM PDT 24
Peak memory 197924 kb
Host smart-9cb3716e-5913-41e2-add8-7ff4cfc9facf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977924851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.1977924851
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.187664416
Short name T841
Test name
Test status
Simulation time 29749335 ps
CPU time 1.32 seconds
Started May 30 01:00:24 PM PDT 24
Finished May 30 01:00:27 PM PDT 24
Peak memory 198008 kb
Host smart-9f32034f-20fc-48ec-a1a7-94484758f116
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187664416 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.187664416
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.795813006
Short name T831
Test name
Test status
Simulation time 22753624 ps
CPU time 0.59 seconds
Started May 30 01:00:08 PM PDT 24
Finished May 30 01:00:09 PM PDT 24
Peak memory 193476 kb
Host smart-4dd15348-f245-4406-ab9a-071ea1dcfbb7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795813006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_
csr_rw.795813006
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.2213600963
Short name T825
Test name
Test status
Simulation time 11790278 ps
CPU time 0.57 seconds
Started May 30 01:00:21 PM PDT 24
Finished May 30 01:00:22 PM PDT 24
Peak memory 194220 kb
Host smart-33698dcf-0885-488a-96d5-35d2f2d2e125
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213600963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.2213600963
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1121179405
Short name T85
Test name
Test status
Simulation time 15616928 ps
CPU time 0.63 seconds
Started May 30 01:00:20 PM PDT 24
Finished May 30 01:00:21 PM PDT 24
Peak memory 194632 kb
Host smart-239886eb-ebb9-4930-879e-e7b00cabc84e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121179405 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.1121179405
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.201737080
Short name T846
Test name
Test status
Simulation time 1618535373 ps
CPU time 2.84 seconds
Started May 30 01:00:22 PM PDT 24
Finished May 30 01:00:26 PM PDT 24
Peak memory 197912 kb
Host smart-82b40b2f-9245-4162-8c1c-eb17c53b4c62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201737080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.201737080
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.305958388
Short name T39
Test name
Test status
Simulation time 80589241 ps
CPU time 0.87 seconds
Started May 30 01:00:09 PM PDT 24
Finished May 30 01:00:11 PM PDT 24
Peak memory 196880 kb
Host smart-fd938468-4fb0-43c4-8344-a32f39f1cb97
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305958388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.gpio_tl_intg_err.305958388
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.306216963
Short name T839
Test name
Test status
Simulation time 55738331 ps
CPU time 0.93 seconds
Started May 30 01:00:16 PM PDT 24
Finished May 30 01:00:18 PM PDT 24
Peak memory 197848 kb
Host smart-b993d9dd-3c9b-423f-ba09-e47aa9ec0b9f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306216963 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.306216963
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.415331866
Short name T786
Test name
Test status
Simulation time 38569712 ps
CPU time 0.58 seconds
Started May 30 01:00:19 PM PDT 24
Finished May 30 01:00:21 PM PDT 24
Peak memory 194588 kb
Host smart-44b8fb5f-2a3f-4a72-abb4-a2adc01dc85d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415331866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_
csr_rw.415331866
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.1069879619
Short name T820
Test name
Test status
Simulation time 14304700 ps
CPU time 0.57 seconds
Started May 30 01:00:27 PM PDT 24
Finished May 30 01:00:29 PM PDT 24
Peak memory 193588 kb
Host smart-b1bf2028-7443-41c8-9fe8-f07807b37cdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069879619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.1069879619
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2805068317
Short name T815
Test name
Test status
Simulation time 16611797 ps
CPU time 0.76 seconds
Started May 30 01:00:23 PM PDT 24
Finished May 30 01:00:25 PM PDT 24
Peak memory 195900 kb
Host smart-89c8129e-9a52-4e55-92fb-6c22ea11e68b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805068317 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.2805068317
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.2900016585
Short name T738
Test name
Test status
Simulation time 54968370 ps
CPU time 2.7 seconds
Started May 30 01:00:30 PM PDT 24
Finished May 30 01:00:34 PM PDT 24
Peak memory 197960 kb
Host smart-679c8f24-d8df-4e36-9259-07302d9d2e75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900016585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.2900016585
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.2092307042
Short name T832
Test name
Test status
Simulation time 146947988 ps
CPU time 1.4 seconds
Started May 30 01:00:15 PM PDT 24
Finished May 30 01:00:17 PM PDT 24
Peak memory 197988 kb
Host smart-5e6e45fb-4227-4aff-aa7e-ad4012632783
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092307042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.2092307042
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.2953763218
Short name T366
Test name
Test status
Simulation time 34480003 ps
CPU time 0.58 seconds
Started May 30 02:30:42 PM PDT 24
Finished May 30 02:30:44 PM PDT 24
Peak memory 193948 kb
Host smart-fcaa322f-00db-48a2-bcc3-f252555d1613
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953763218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.2953763218
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.1681944619
Short name T135
Test name
Test status
Simulation time 30638826 ps
CPU time 0.91 seconds
Started May 30 02:30:34 PM PDT 24
Finished May 30 02:30:36 PM PDT 24
Peak memory 196660 kb
Host smart-7bef178c-80a8-41be-82e2-8a528091de9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681944619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.1681944619
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.450752682
Short name T313
Test name
Test status
Simulation time 1926792940 ps
CPU time 10.63 seconds
Started May 30 02:30:34 PM PDT 24
Finished May 30 02:30:46 PM PDT 24
Peak memory 195576 kb
Host smart-ada505c5-c2f9-4a96-a089-2900fbdb8026
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450752682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stress
.450752682
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.3026724764
Short name T591
Test name
Test status
Simulation time 42798432 ps
CPU time 0.82 seconds
Started May 30 02:30:33 PM PDT 24
Finished May 30 02:30:35 PM PDT 24
Peak memory 196840 kb
Host smart-bd545bf7-efc6-4297-bbcc-96cc561371f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026724764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.3026724764
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.2048356078
Short name T613
Test name
Test status
Simulation time 236893985 ps
CPU time 0.98 seconds
Started May 30 02:30:30 PM PDT 24
Finished May 30 02:30:32 PM PDT 24
Peak memory 196140 kb
Host smart-356273ef-58ba-4ff1-bd82-ba6a83d92de0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048356078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.2048356078
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.450932877
Short name T645
Test name
Test status
Simulation time 115954944 ps
CPU time 1.44 seconds
Started May 30 02:30:31 PM PDT 24
Finished May 30 02:30:33 PM PDT 24
Peak memory 197844 kb
Host smart-7e641181-5bec-43ee-8d6c-336ad7088caa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450932877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.gpio_intr_with_filter_rand_intr_event.450932877
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.3853683733
Short name T149
Test name
Test status
Simulation time 131756213 ps
CPU time 1.19 seconds
Started May 30 02:30:33 PM PDT 24
Finished May 30 02:30:36 PM PDT 24
Peak memory 196196 kb
Host smart-93b65352-64c4-4e94-96a2-894cdcdeda11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853683733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
3853683733
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.2070684424
Short name T601
Test name
Test status
Simulation time 28654446 ps
CPU time 1.1 seconds
Started May 30 02:30:34 PM PDT 24
Finished May 30 02:30:37 PM PDT 24
Peak memory 195856 kb
Host smart-2714b75b-c7ce-473d-97f8-4b2c40bc8aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070684424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.2070684424
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.1062580838
Short name T474
Test name
Test status
Simulation time 206127239 ps
CPU time 1.03 seconds
Started May 30 02:30:33 PM PDT 24
Finished May 30 02:30:35 PM PDT 24
Peak memory 195908 kb
Host smart-8f6ae3ab-9868-4197-87fe-b02427c17f44
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062580838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.1062580838
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.3470793291
Short name T152
Test name
Test status
Simulation time 3698727892 ps
CPU time 3.24 seconds
Started May 30 02:30:30 PM PDT 24
Finished May 30 02:30:35 PM PDT 24
Peak memory 198180 kb
Host smart-5bc2955e-8fe3-482f-9241-e3e9c6c674c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470793291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.3470793291
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.3290899505
Short name T58
Test name
Test status
Simulation time 85656323 ps
CPU time 0.9 seconds
Started May 30 02:30:47 PM PDT 24
Finished May 30 02:30:50 PM PDT 24
Peak memory 213796 kb
Host smart-81447b5e-c066-42ad-b48e-94b36cdfe449
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290899505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.3290899505
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.1637160735
Short name T337
Test name
Test status
Simulation time 172727530 ps
CPU time 1.27 seconds
Started May 30 02:30:30 PM PDT 24
Finished May 30 02:30:33 PM PDT 24
Peak memory 196796 kb
Host smart-9adbf7ec-4419-4784-8c2d-fb7d6d0aa322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637160735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1637160735
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.1954349626
Short name T348
Test name
Test status
Simulation time 136895350 ps
CPU time 1.03 seconds
Started May 30 02:30:34 PM PDT 24
Finished May 30 02:30:37 PM PDT 24
Peak memory 196564 kb
Host smart-18bf674c-36f8-46cb-808c-631785975587
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954349626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.1954349626
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.436797696
Short name T307
Test name
Test status
Simulation time 19770623534 ps
CPU time 40.24 seconds
Started May 30 02:30:34 PM PDT 24
Finished May 30 02:31:15 PM PDT 24
Peak memory 198208 kb
Host smart-942660f7-0360-4e7e-9539-fd6f064bac5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436797696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gp
io_stress_all.436797696
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.1732794852
Short name T66
Test name
Test status
Simulation time 39478863 ps
CPU time 0.6 seconds
Started May 30 02:30:41 PM PDT 24
Finished May 30 02:30:43 PM PDT 24
Peak memory 194100 kb
Host smart-206c77dd-3f42-463a-901e-ed29c12e179f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732794852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.1732794852
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.3383082603
Short name T510
Test name
Test status
Simulation time 28210068 ps
CPU time 0.73 seconds
Started May 30 02:30:41 PM PDT 24
Finished May 30 02:30:43 PM PDT 24
Peak memory 196068 kb
Host smart-94edcc18-8b39-41c6-8edf-e3fb77f1c9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383082603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.3383082603
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.3718420588
Short name T498
Test name
Test status
Simulation time 116280307 ps
CPU time 5.97 seconds
Started May 30 02:30:40 PM PDT 24
Finished May 30 02:30:48 PM PDT 24
Peak memory 196964 kb
Host smart-19b89a38-4641-4b3a-bb8a-6bcdf971924f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718420588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.3718420588
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.2150500880
Short name T216
Test name
Test status
Simulation time 36708182 ps
CPU time 0.75 seconds
Started May 30 02:30:39 PM PDT 24
Finished May 30 02:30:41 PM PDT 24
Peak memory 195916 kb
Host smart-77bffb29-4023-4208-a8ed-597ad88678b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150500880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.2150500880
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.489032203
Short name T373
Test name
Test status
Simulation time 51582501 ps
CPU time 0.95 seconds
Started May 30 02:30:41 PM PDT 24
Finished May 30 02:30:43 PM PDT 24
Peak memory 197484 kb
Host smart-7225aee7-653d-429f-bfaa-1db7e23a8e42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489032203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.489032203
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.3788038714
Short name T603
Test name
Test status
Simulation time 349494224 ps
CPU time 1.85 seconds
Started May 30 02:30:43 PM PDT 24
Finished May 30 02:30:46 PM PDT 24
Peak memory 198136 kb
Host smart-e4afce71-6634-4b5c-90fe-385143026a36
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788038714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.3788038714
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.2748491577
Short name T419
Test name
Test status
Simulation time 136102377 ps
CPU time 1.98 seconds
Started May 30 02:30:39 PM PDT 24
Finished May 30 02:30:42 PM PDT 24
Peak memory 195924 kb
Host smart-d4e6a510-7274-40ac-ab13-a5c918cf0acd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748491577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
2748491577
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.3482908553
Short name T333
Test name
Test status
Simulation time 101690133 ps
CPU time 0.71 seconds
Started May 30 02:30:40 PM PDT 24
Finished May 30 02:30:42 PM PDT 24
Peak memory 195100 kb
Host smart-fc2eeb3b-9188-43cc-94a6-4775a094b59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482908553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.3482908553
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.3293852406
Short name T180
Test name
Test status
Simulation time 161057514 ps
CPU time 1.19 seconds
Started May 30 02:30:47 PM PDT 24
Finished May 30 02:30:50 PM PDT 24
Peak memory 196612 kb
Host smart-f66f77c7-cdaf-4e5c-ad09-eccac65caa8d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293852406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.3293852406
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.2893234368
Short name T228
Test name
Test status
Simulation time 154890892 ps
CPU time 3.65 seconds
Started May 30 02:30:41 PM PDT 24
Finished May 30 02:30:46 PM PDT 24
Peak memory 197924 kb
Host smart-e0c38971-7314-4536-9e29-3b7ba7282920
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893234368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.2893234368
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.3369332173
Short name T57
Test name
Test status
Simulation time 174577229 ps
CPU time 0.86 seconds
Started May 30 02:30:39 PM PDT 24
Finished May 30 02:30:41 PM PDT 24
Peak memory 213856 kb
Host smart-c0655db8-a92a-4e46-9dcf-326136c4e808
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369332173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.3369332173
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.2671713384
Short name T194
Test name
Test status
Simulation time 76517482 ps
CPU time 0.79 seconds
Started May 30 02:30:38 PM PDT 24
Finished May 30 02:30:40 PM PDT 24
Peak memory 196024 kb
Host smart-6d420626-35d3-4db0-8bc9-2c2eb7373f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671713384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2671713384
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.777247856
Short name T563
Test name
Test status
Simulation time 273875688 ps
CPU time 1.41 seconds
Started May 30 02:30:41 PM PDT 24
Finished May 30 02:30:44 PM PDT 24
Peak memory 196780 kb
Host smart-638f253e-1124-42a8-acba-58b8320a45d7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777247856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.777247856
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.4152213151
Short name T494
Test name
Test status
Simulation time 11522148739 ps
CPU time 164.15 seconds
Started May 30 02:30:40 PM PDT 24
Finished May 30 02:33:26 PM PDT 24
Peak memory 198200 kb
Host smart-657bd1be-2e2d-49a0-8d61-806752d3c825
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152213151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.4152213151
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.411522915
Short name T651
Test name
Test status
Simulation time 57291913512 ps
CPU time 251.86 seconds
Started May 30 02:30:41 PM PDT 24
Finished May 30 02:34:54 PM PDT 24
Peak memory 198280 kb
Host smart-b181dba9-1423-45c9-8f62-b71ceeaef038
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=411522915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.411522915
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.2236828042
Short name T552
Test name
Test status
Simulation time 13650011 ps
CPU time 0.6 seconds
Started May 30 02:31:13 PM PDT 24
Finished May 30 02:31:15 PM PDT 24
Peak memory 194836 kb
Host smart-7e0fb85a-1b91-42b7-a7c2-44bc7b7cd3a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236828042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.2236828042
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.2667198687
Short name T684
Test name
Test status
Simulation time 17481339 ps
CPU time 0.62 seconds
Started May 30 02:31:12 PM PDT 24
Finished May 30 02:31:13 PM PDT 24
Peak memory 193940 kb
Host smart-8b47b934-9414-4848-bb4f-cfbd8d84e819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667198687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.2667198687
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.1293257371
Short name T382
Test name
Test status
Simulation time 349972953 ps
CPU time 5.18 seconds
Started May 30 02:31:16 PM PDT 24
Finished May 30 02:31:24 PM PDT 24
Peak memory 195652 kb
Host smart-6167e7ee-47bf-4be5-86bf-88b30262664f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293257371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.1293257371
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.114640722
Short name T13
Test name
Test status
Simulation time 47898110 ps
CPU time 0.84 seconds
Started May 30 02:31:12 PM PDT 24
Finished May 30 02:31:14 PM PDT 24
Peak memory 196108 kb
Host smart-af957328-b42c-4ef9-a0dc-a5070a0a7f2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114640722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.114640722
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.2091472670
Short name T713
Test name
Test status
Simulation time 106137291 ps
CPU time 1.09 seconds
Started May 30 02:31:15 PM PDT 24
Finished May 30 02:31:18 PM PDT 24
Peak memory 196140 kb
Host smart-4fced149-6444-47df-aca8-a753e95232c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091472670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.2091472670
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.3366178005
Short name T501
Test name
Test status
Simulation time 249420342 ps
CPU time 2.07 seconds
Started May 30 02:31:15 PM PDT 24
Finished May 30 02:31:20 PM PDT 24
Peak memory 198128 kb
Host smart-31efe0fe-046b-4547-b8cb-1861653544c8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366178005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.3366178005
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.794381669
Short name T433
Test name
Test status
Simulation time 91753181 ps
CPU time 2.14 seconds
Started May 30 02:31:10 PM PDT 24
Finished May 30 02:31:13 PM PDT 24
Peak memory 196244 kb
Host smart-2a0e7e59-9258-45e7-8234-c6b792819875
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794381669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger.
794381669
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.2530017683
Short name T361
Test name
Test status
Simulation time 119761790 ps
CPU time 1.44 seconds
Started May 30 02:31:13 PM PDT 24
Finished May 30 02:31:16 PM PDT 24
Peak memory 197244 kb
Host smart-c14c2572-1f63-4a76-b5a8-5eebd2311158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530017683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.2530017683
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.225241904
Short name T639
Test name
Test status
Simulation time 386101308 ps
CPU time 1.01 seconds
Started May 30 02:31:13 PM PDT 24
Finished May 30 02:31:16 PM PDT 24
Peak memory 196048 kb
Host smart-dd295128-ea5f-44ab-bef6-61da3878be2a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225241904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullup
_pulldown.225241904
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.3078367616
Short name T77
Test name
Test status
Simulation time 301352832 ps
CPU time 3.8 seconds
Started May 30 02:31:13 PM PDT 24
Finished May 30 02:31:18 PM PDT 24
Peak memory 198076 kb
Host smart-f5a553de-8104-4b5f-8357-411052ca45c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078367616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.3078367616
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.513980111
Short name T633
Test name
Test status
Simulation time 36951478 ps
CPU time 1.2 seconds
Started May 30 02:31:12 PM PDT 24
Finished May 30 02:31:14 PM PDT 24
Peak memory 196472 kb
Host smart-53962a56-4227-4ca2-91c6-956f8e53fc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513980111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.513980111
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.1834201818
Short name T521
Test name
Test status
Simulation time 90641186 ps
CPU time 1.41 seconds
Started May 30 02:31:11 PM PDT 24
Finished May 30 02:31:14 PM PDT 24
Peak memory 196760 kb
Host smart-a9083f42-93a6-4fbd-a098-cce80d49796e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834201818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.1834201818
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.217605884
Short name T260
Test name
Test status
Simulation time 45049322165 ps
CPU time 34.46 seconds
Started May 30 02:31:12 PM PDT 24
Finished May 30 02:31:48 PM PDT 24
Peak memory 198232 kb
Host smart-25bab179-de54-491d-9789-72f6b66c3ed9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217605884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.g
pio_stress_all.217605884
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.2157337076
Short name T105
Test name
Test status
Simulation time 73925999292 ps
CPU time 1467.15 seconds
Started May 30 02:31:14 PM PDT 24
Finished May 30 02:55:44 PM PDT 24
Peak memory 198368 kb
Host smart-48b60e9c-fb4e-45a0-a8ef-0c2045198f41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2157337076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.2157337076
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.2209809283
Short name T626
Test name
Test status
Simulation time 11369631 ps
CPU time 0.55 seconds
Started May 30 02:31:15 PM PDT 24
Finished May 30 02:31:18 PM PDT 24
Peak memory 192752 kb
Host smart-2cea2fa6-7e02-448e-b5cc-739d198ee73b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209809283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.2209809283
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.3754031374
Short name T207
Test name
Test status
Simulation time 89997459 ps
CPU time 0.92 seconds
Started May 30 02:31:12 PM PDT 24
Finished May 30 02:31:14 PM PDT 24
Peak memory 196556 kb
Host smart-769a96f7-8cf8-414a-98f9-6bca4d2b99cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754031374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.3754031374
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.958199622
Short name T716
Test name
Test status
Simulation time 486955401 ps
CPU time 12.06 seconds
Started May 30 02:31:13 PM PDT 24
Finished May 30 02:31:26 PM PDT 24
Peak memory 196352 kb
Host smart-190307c6-f4ae-4266-957f-2a6c482d8ae9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958199622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stres
s.958199622
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.447982333
Short name T347
Test name
Test status
Simulation time 101036695 ps
CPU time 0.71 seconds
Started May 30 02:31:15 PM PDT 24
Finished May 30 02:31:18 PM PDT 24
Peak memory 195432 kb
Host smart-9cad7289-7b62-4e17-82af-08b025f6316f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447982333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.447982333
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.324508554
Short name T328
Test name
Test status
Simulation time 376685518 ps
CPU time 1.36 seconds
Started May 30 02:31:15 PM PDT 24
Finished May 30 02:31:19 PM PDT 24
Peak memory 197308 kb
Host smart-26a1d8c5-87ae-48da-95ce-0c50b87097f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324508554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.324508554
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.4198668175
Short name T219
Test name
Test status
Simulation time 233810125 ps
CPU time 1.3 seconds
Started May 30 02:31:15 PM PDT 24
Finished May 30 02:31:18 PM PDT 24
Peak memory 196928 kb
Host smart-e31c9f3a-749e-437c-afb7-2e330bc0a386
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198668175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.4198668175
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.4265560692
Short name T262
Test name
Test status
Simulation time 172147435 ps
CPU time 1.7 seconds
Started May 30 02:31:15 PM PDT 24
Finished May 30 02:31:20 PM PDT 24
Peak memory 196196 kb
Host smart-d29e6052-943e-4c04-b140-47c124cd54c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265560692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.4265560692
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.3981064164
Short name T677
Test name
Test status
Simulation time 61059721 ps
CPU time 0.62 seconds
Started May 30 02:31:15 PM PDT 24
Finished May 30 02:31:18 PM PDT 24
Peak memory 194344 kb
Host smart-c28d4fd0-fb4e-4102-8789-87a743634b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981064164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.3981064164
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.2255898449
Short name T395
Test name
Test status
Simulation time 21982255 ps
CPU time 0.91 seconds
Started May 30 02:31:15 PM PDT 24
Finished May 30 02:31:19 PM PDT 24
Peak memory 196028 kb
Host smart-365ce81f-cc08-407b-b108-ddac25eca50c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255898449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.2255898449
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.1483787536
Short name T21
Test name
Test status
Simulation time 2345572793 ps
CPU time 5.96 seconds
Started May 30 02:31:14 PM PDT 24
Finished May 30 02:31:22 PM PDT 24
Peak memory 198128 kb
Host smart-bef70665-3f3a-4e60-ba94-bc31ca40a9fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483787536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.1483787536
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.4050685354
Short name T379
Test name
Test status
Simulation time 154006897 ps
CPU time 1.2 seconds
Started May 30 02:31:12 PM PDT 24
Finished May 30 02:31:15 PM PDT 24
Peak memory 195932 kb
Host smart-3a38934a-4904-4252-bed9-e8cbf7cb929e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050685354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.4050685354
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.4193525685
Short name T386
Test name
Test status
Simulation time 71098401 ps
CPU time 1.12 seconds
Started May 30 02:31:13 PM PDT 24
Finished May 30 02:31:16 PM PDT 24
Peak memory 195560 kb
Host smart-34e59cbc-0c7b-416d-b761-cd35a7459527
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193525685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.4193525685
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.2116386872
Short name T185
Test name
Test status
Simulation time 10119430859 ps
CPU time 144.91 seconds
Started May 30 02:31:16 PM PDT 24
Finished May 30 02:33:44 PM PDT 24
Peak memory 198312 kb
Host smart-f71b06f4-8032-427b-a1d9-bff6024a2140
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116386872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.2116386872
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.2018564676
Short name T431
Test name
Test status
Simulation time 455417918775 ps
CPU time 1391.41 seconds
Started May 30 02:31:14 PM PDT 24
Finished May 30 02:54:27 PM PDT 24
Peak memory 198356 kb
Host smart-caf73942-f7b6-424f-977d-77e0a110457f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2018564676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.2018564676
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.4072232952
Short name T479
Test name
Test status
Simulation time 32452104 ps
CPU time 0.59 seconds
Started May 30 02:31:12 PM PDT 24
Finished May 30 02:31:14 PM PDT 24
Peak memory 193916 kb
Host smart-be0529c0-ec79-4757-bc21-acc1ffb2bf21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072232952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.4072232952
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.1072622395
Short name T455
Test name
Test status
Simulation time 28509378 ps
CPU time 0.85 seconds
Started May 30 02:31:13 PM PDT 24
Finished May 30 02:31:15 PM PDT 24
Peak memory 196124 kb
Host smart-e88136dd-741f-4474-a0cc-feb980f5aafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072622395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.1072622395
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.894697753
Short name T629
Test name
Test status
Simulation time 8434438669 ps
CPU time 21.93 seconds
Started May 30 02:31:15 PM PDT 24
Finished May 30 02:31:39 PM PDT 24
Peak memory 198228 kb
Host smart-4c8ca1ae-1cfa-4542-886c-8c36daae6a2f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894697753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stres
s.894697753
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.4219123357
Short name T128
Test name
Test status
Simulation time 299219279 ps
CPU time 0.95 seconds
Started May 30 02:31:14 PM PDT 24
Finished May 30 02:31:18 PM PDT 24
Peak memory 197208 kb
Host smart-c10ed3dd-5842-4849-8dca-4cc49be956c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219123357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.4219123357
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.2406462722
Short name T447
Test name
Test status
Simulation time 85474032 ps
CPU time 0.88 seconds
Started May 30 02:31:13 PM PDT 24
Finished May 30 02:31:15 PM PDT 24
Peak memory 195688 kb
Host smart-d0701734-a53f-4f60-8730-5c5c703a8d84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406462722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.2406462722
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.1237796219
Short name T187
Test name
Test status
Simulation time 59765740 ps
CPU time 2.43 seconds
Started May 30 02:31:15 PM PDT 24
Finished May 30 02:31:19 PM PDT 24
Peak memory 196592 kb
Host smart-8957b50f-800b-4aef-a1b4-8fafd3c7bfaa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237796219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.1237796219
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.892243729
Short name T695
Test name
Test status
Simulation time 241248880 ps
CPU time 2.97 seconds
Started May 30 02:31:15 PM PDT 24
Finished May 30 02:31:20 PM PDT 24
Peak memory 198108 kb
Host smart-61672a9c-806f-4b09-9c3c-a5123835a599
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892243729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger.
892243729
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.1761305536
Short name T459
Test name
Test status
Simulation time 35339967 ps
CPU time 0.98 seconds
Started May 30 02:31:13 PM PDT 24
Finished May 30 02:31:16 PM PDT 24
Peak memory 195864 kb
Host smart-9b52c618-2fe4-4cad-9c16-f21cc0f8b572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761305536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.1761305536
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.3387421063
Short name T151
Test name
Test status
Simulation time 41391522 ps
CPU time 0.66 seconds
Started May 30 02:31:15 PM PDT 24
Finished May 30 02:31:19 PM PDT 24
Peak memory 194464 kb
Host smart-3cbc4131-f2bf-4a9b-84c9-960cbeb5f775
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387421063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.3387421063
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.123868744
Short name T292
Test name
Test status
Simulation time 269258772 ps
CPU time 1.67 seconds
Started May 30 02:31:15 PM PDT 24
Finished May 30 02:31:20 PM PDT 24
Peak memory 197848 kb
Host smart-a8f28cca-2f33-4c12-92c8-d846e04bc86c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123868744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ran
dom_long_reg_writes_reg_reads.123868744
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.224102989
Short name T410
Test name
Test status
Simulation time 73953071 ps
CPU time 1.17 seconds
Started May 30 02:31:13 PM PDT 24
Finished May 30 02:31:15 PM PDT 24
Peak memory 195600 kb
Host smart-f69f6385-7828-4372-98ed-32c02c55ea1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224102989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.224102989
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.1847097118
Short name T536
Test name
Test status
Simulation time 109249609 ps
CPU time 1.2 seconds
Started May 30 02:31:13 PM PDT 24
Finished May 30 02:31:16 PM PDT 24
Peak memory 195832 kb
Host smart-a4ab5728-34f7-42db-a7ac-3bad2bef209d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847097118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.1847097118
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.1353925412
Short name T458
Test name
Test status
Simulation time 5035915290 ps
CPU time 27.23 seconds
Started May 30 02:31:15 PM PDT 24
Finished May 30 02:31:45 PM PDT 24
Peak memory 198344 kb
Host smart-154443b6-daa5-4e8a-88b7-21fa494db018
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353925412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.1353925412
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.1194896339
Short name T471
Test name
Test status
Simulation time 15697292 ps
CPU time 0.62 seconds
Started May 30 02:31:13 PM PDT 24
Finished May 30 02:31:15 PM PDT 24
Peak memory 194148 kb
Host smart-c6e95ce0-8061-4e0c-9b36-81a0ef93a9a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194896339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.1194896339
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.3940024729
Short name T532
Test name
Test status
Simulation time 19310726 ps
CPU time 0.67 seconds
Started May 30 02:31:12 PM PDT 24
Finished May 30 02:31:15 PM PDT 24
Peak memory 194796 kb
Host smart-5e23591f-a21a-4757-95a7-fb5e46e79e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940024729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.3940024729
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.1775071341
Short name T389
Test name
Test status
Simulation time 166900532 ps
CPU time 5.05 seconds
Started May 30 02:31:16 PM PDT 24
Finished May 30 02:31:24 PM PDT 24
Peak memory 196060 kb
Host smart-37b692a3-56c0-45df-9392-75de2b9019f6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775071341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.1775071341
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.3605558929
Short name T707
Test name
Test status
Simulation time 119494490 ps
CPU time 0.9 seconds
Started May 30 02:31:17 PM PDT 24
Finished May 30 02:31:20 PM PDT 24
Peak memory 197992 kb
Host smart-8f11c6ab-b199-460c-b805-de3d1ea02e23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605558929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.3605558929
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.3670196921
Short name T483
Test name
Test status
Simulation time 51897080 ps
CPU time 1.11 seconds
Started May 30 02:31:16 PM PDT 24
Finished May 30 02:31:20 PM PDT 24
Peak memory 196256 kb
Host smart-68561e32-c319-431d-aa82-c9e57c0f5789
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670196921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.3670196921
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.1466436356
Short name T556
Test name
Test status
Simulation time 225029828 ps
CPU time 2.87 seconds
Started May 30 02:31:15 PM PDT 24
Finished May 30 02:31:21 PM PDT 24
Peak memory 197212 kb
Host smart-68ac563f-c1dc-49ce-8350-ce849b4ed29c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466436356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.1466436356
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.3169347863
Short name T683
Test name
Test status
Simulation time 93791006 ps
CPU time 0.85 seconds
Started May 30 02:31:14 PM PDT 24
Finished May 30 02:31:17 PM PDT 24
Peak memory 194552 kb
Host smart-db87413a-177f-4c0a-8d6d-12e48ada5072
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169347863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.3169347863
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.1894134388
Short name T568
Test name
Test status
Simulation time 174458581 ps
CPU time 0.83 seconds
Started May 30 02:31:17 PM PDT 24
Finished May 30 02:31:21 PM PDT 24
Peak memory 195616 kb
Host smart-0d780857-31b2-4dac-a209-1a238a4d6e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894134388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.1894134388
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.1517130539
Short name T691
Test name
Test status
Simulation time 72608410 ps
CPU time 0.87 seconds
Started May 30 02:31:17 PM PDT 24
Finished May 30 02:31:20 PM PDT 24
Peak memory 196684 kb
Host smart-a726cd71-540c-464e-8f80-934df4f32c30
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517130539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.1517130539
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.2518125558
Short name T572
Test name
Test status
Simulation time 312892979 ps
CPU time 3.81 seconds
Started May 30 02:31:14 PM PDT 24
Finished May 30 02:31:21 PM PDT 24
Peak memory 198000 kb
Host smart-b34cdf38-a780-4bda-8608-039ab2422b40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518125558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.2518125558
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.894396223
Short name T341
Test name
Test status
Simulation time 175784435 ps
CPU time 1.09 seconds
Started May 30 02:31:16 PM PDT 24
Finished May 30 02:31:20 PM PDT 24
Peak memory 196444 kb
Host smart-711aaf26-f763-4d14-808e-c39e09a806b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894396223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.894396223
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.439023788
Short name T202
Test name
Test status
Simulation time 307782109 ps
CPU time 1.64 seconds
Started May 30 02:31:17 PM PDT 24
Finished May 30 02:31:21 PM PDT 24
Peak memory 196868 kb
Host smart-8521946b-27eb-4028-8569-8d2e45f4fb51
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439023788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.439023788
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_alert_test.2000660952
Short name T434
Test name
Test status
Simulation time 167604336 ps
CPU time 0.59 seconds
Started May 30 02:31:30 PM PDT 24
Finished May 30 02:31:31 PM PDT 24
Peak memory 194648 kb
Host smart-64e741f5-30d6-4158-b202-53d6a17a028e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000660952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.2000660952
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.2986612762
Short name T377
Test name
Test status
Simulation time 42434354 ps
CPU time 0.95 seconds
Started May 30 02:31:28 PM PDT 24
Finished May 30 02:31:30 PM PDT 24
Peak memory 196468 kb
Host smart-e95ec17c-fa6c-4538-82d4-d96998e89ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986612762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.2986612762
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.2786775182
Short name T35
Test name
Test status
Simulation time 367227027 ps
CPU time 19.91 seconds
Started May 30 02:31:30 PM PDT 24
Finished May 30 02:31:51 PM PDT 24
Peak memory 196940 kb
Host smart-32475ccd-df5a-4f15-9d02-d83553175384
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786775182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.2786775182
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.4102507040
Short name T312
Test name
Test status
Simulation time 179429923 ps
CPU time 1.05 seconds
Started May 30 02:31:27 PM PDT 24
Finished May 30 02:31:28 PM PDT 24
Peak memory 197888 kb
Host smart-f3424738-e81a-460d-929f-46865fd85c0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102507040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.4102507040
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.3425056557
Short name T675
Test name
Test status
Simulation time 96993861 ps
CPU time 1.31 seconds
Started May 30 02:31:34 PM PDT 24
Finished May 30 02:31:37 PM PDT 24
Peak memory 197164 kb
Host smart-b7e9bc55-4381-44d5-a93b-07efc427dfd9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425056557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.3425056557
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3364639494
Short name T634
Test name
Test status
Simulation time 136891775 ps
CPU time 2.97 seconds
Started May 30 02:31:31 PM PDT 24
Finished May 30 02:31:36 PM PDT 24
Peak memory 198108 kb
Host smart-f0501a69-9ff4-4241-9814-b5f1df771128
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364639494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3364639494
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.387109828
Short name T140
Test name
Test status
Simulation time 229764280 ps
CPU time 3.07 seconds
Started May 30 02:31:34 PM PDT 24
Finished May 30 02:31:39 PM PDT 24
Peak memory 195604 kb
Host smart-e1e03941-cdb1-4e84-856f-c644d2d4b998
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387109828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger.
387109828
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.3309990786
Short name T562
Test name
Test status
Simulation time 20537803 ps
CPU time 0.72 seconds
Started May 30 02:31:17 PM PDT 24
Finished May 30 02:31:20 PM PDT 24
Peak memory 194456 kb
Host smart-1c7766bf-e40c-4f42-9d23-978386d900ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309990786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.3309990786
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.3696757262
Short name T381
Test name
Test status
Simulation time 267636838 ps
CPU time 1 seconds
Started May 30 02:31:17 PM PDT 24
Finished May 30 02:31:21 PM PDT 24
Peak memory 196012 kb
Host smart-f6ae5937-ab72-444e-ace2-998f7f926885
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696757262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.3696757262
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.1661628756
Short name T618
Test name
Test status
Simulation time 298295899 ps
CPU time 3.51 seconds
Started May 30 02:31:26 PM PDT 24
Finished May 30 02:31:30 PM PDT 24
Peak memory 198044 kb
Host smart-06022e07-03ee-4cd7-9a12-544ec7de8d49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661628756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.1661628756
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.2601807616
Short name T640
Test name
Test status
Simulation time 92433281 ps
CPU time 0.85 seconds
Started May 30 02:31:16 PM PDT 24
Finished May 30 02:31:20 PM PDT 24
Peak memory 196520 kb
Host smart-7dc89744-caf2-48b3-806a-4dc6c3bf2c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601807616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.2601807616
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.2357314993
Short name T456
Test name
Test status
Simulation time 162284697 ps
CPU time 1.27 seconds
Started May 30 02:31:16 PM PDT 24
Finished May 30 02:31:20 PM PDT 24
Peak memory 196364 kb
Host smart-e40365fc-ae2f-4f86-aa77-356fd0588a1f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357314993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.2357314993
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.1037750290
Short name T111
Test name
Test status
Simulation time 37135663108 ps
CPU time 166.49 seconds
Started May 30 02:31:28 PM PDT 24
Finished May 30 02:34:15 PM PDT 24
Peak memory 198256 kb
Host smart-fb800b2f-993e-4f50-9c62-0577e11969b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037750290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.1037750290
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.3292531306
Short name T64
Test name
Test status
Simulation time 22151228 ps
CPU time 0.63 seconds
Started May 30 02:31:29 PM PDT 24
Finished May 30 02:31:31 PM PDT 24
Peak memory 194172 kb
Host smart-aab60a4f-1a41-4504-9511-7963296c3242
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292531306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.3292531306
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.2873269850
Short name T332
Test name
Test status
Simulation time 307794755 ps
CPU time 0.78 seconds
Started May 30 02:31:26 PM PDT 24
Finished May 30 02:31:27 PM PDT 24
Peak memory 195480 kb
Host smart-7bca60b6-11f8-448b-97fa-87bf60a8a1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873269850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.2873269850
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.4225167984
Short name T281
Test name
Test status
Simulation time 394721591 ps
CPU time 19.9 seconds
Started May 30 02:31:30 PM PDT 24
Finished May 30 02:31:51 PM PDT 24
Peak memory 197176 kb
Host smart-59dc82ff-24fb-44db-8563-4c89792dd31e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225167984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.4225167984
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.810564847
Short name T236
Test name
Test status
Simulation time 185787181 ps
CPU time 0.8 seconds
Started May 30 02:31:34 PM PDT 24
Finished May 30 02:31:37 PM PDT 24
Peak memory 196016 kb
Host smart-eadb2571-6c92-429f-95f2-0084886c6ae3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810564847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.810564847
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.217276778
Short name T668
Test name
Test status
Simulation time 96114153 ps
CPU time 1.38 seconds
Started May 30 02:31:25 PM PDT 24
Finished May 30 02:31:27 PM PDT 24
Peak memory 198104 kb
Host smart-b9522433-76d1-4c00-9945-d3350a22b4f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217276778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.217276778
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.385383849
Short name T428
Test name
Test status
Simulation time 101605478 ps
CPU time 1.24 seconds
Started May 30 02:31:34 PM PDT 24
Finished May 30 02:31:37 PM PDT 24
Peak memory 197908 kb
Host smart-e81fbc3d-b101-4255-8a3f-9cd151882825
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385383849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.gpio_intr_with_filter_rand_intr_event.385383849
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.869805063
Short name T252
Test name
Test status
Simulation time 206297684 ps
CPU time 1.57 seconds
Started May 30 02:31:26 PM PDT 24
Finished May 30 02:31:28 PM PDT 24
Peak memory 195820 kb
Host smart-8f6aff84-0b9a-4632-8d8e-937bb8479bd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869805063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger.
869805063
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.1368455496
Short name T506
Test name
Test status
Simulation time 94144051 ps
CPU time 1.09 seconds
Started May 30 02:31:26 PM PDT 24
Finished May 30 02:31:28 PM PDT 24
Peak memory 196140 kb
Host smart-c27560fa-f622-45db-bfdb-5343465305a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368455496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.1368455496
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.505261092
Short name T280
Test name
Test status
Simulation time 111077452 ps
CPU time 0.87 seconds
Started May 30 02:31:31 PM PDT 24
Finished May 30 02:31:34 PM PDT 24
Peak memory 197480 kb
Host smart-0b35a077-951c-495d-8154-3d9ae9ac7658
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505261092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullup
_pulldown.505261092
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.841033452
Short name T331
Test name
Test status
Simulation time 656191956 ps
CPU time 3.76 seconds
Started May 30 02:31:30 PM PDT 24
Finished May 30 02:31:35 PM PDT 24
Peak memory 197948 kb
Host smart-f17d9edb-c57b-447e-8e0b-aa908e5fdb64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841033452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ran
dom_long_reg_writes_reg_reads.841033452
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.2857792982
Short name T30
Test name
Test status
Simulation time 23410890 ps
CPU time 0.83 seconds
Started May 30 02:31:28 PM PDT 24
Finished May 30 02:31:30 PM PDT 24
Peak memory 196080 kb
Host smart-cf234ae9-ded3-44e8-a908-ecd62513c0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857792982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.2857792982
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.4255123855
Short name T665
Test name
Test status
Simulation time 55272083 ps
CPU time 0.89 seconds
Started May 30 02:31:27 PM PDT 24
Finished May 30 02:31:28 PM PDT 24
Peak memory 196116 kb
Host smart-3700dcd9-ee71-410f-b534-76e00f039948
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255123855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.4255123855
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.991851561
Short name T438
Test name
Test status
Simulation time 18140775883 ps
CPU time 127.22 seconds
Started May 30 02:31:35 PM PDT 24
Finished May 30 02:33:44 PM PDT 24
Peak memory 198232 kb
Host smart-2d1ef3d5-153c-4ff5-b5ca-b4fe900d2339
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991851561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.g
pio_stress_all.991851561
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.1729017112
Short name T602
Test name
Test status
Simulation time 25910262046 ps
CPU time 201.58 seconds
Started May 30 02:31:28 PM PDT 24
Finished May 30 02:34:51 PM PDT 24
Peak memory 198264 kb
Host smart-60ddbd43-e32a-4a15-b1d8-c370cabe72f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1729017112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.1729017112
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.1964756513
Short name T517
Test name
Test status
Simulation time 40715915 ps
CPU time 0.57 seconds
Started May 30 02:31:30 PM PDT 24
Finished May 30 02:31:31 PM PDT 24
Peak memory 193896 kb
Host smart-35d27e3b-d8ef-4191-b2d2-87c546a912c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964756513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.1964756513
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.1528304994
Short name T320
Test name
Test status
Simulation time 114448803 ps
CPU time 0.79 seconds
Started May 30 02:31:27 PM PDT 24
Finished May 30 02:31:28 PM PDT 24
Peak memory 196140 kb
Host smart-cc165fec-8a42-44cf-a2b1-716137855bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528304994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.1528304994
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.1607829806
Short name T429
Test name
Test status
Simulation time 767925514 ps
CPU time 18.79 seconds
Started May 30 02:31:35 PM PDT 24
Finished May 30 02:31:55 PM PDT 24
Peak memory 195560 kb
Host smart-1b844efb-0a84-4fdb-97ac-af118de3587b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607829806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.1607829806
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.1903716748
Short name T577
Test name
Test status
Simulation time 195914714 ps
CPU time 0.91 seconds
Started May 30 02:31:29 PM PDT 24
Finished May 30 02:31:31 PM PDT 24
Peak memory 196340 kb
Host smart-a3acf437-6651-45a8-b130-09232b224d2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903716748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.1903716748
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.240216975
Short name T78
Test name
Test status
Simulation time 87488179 ps
CPU time 1.29 seconds
Started May 30 02:31:25 PM PDT 24
Finished May 30 02:31:27 PM PDT 24
Peak memory 197268 kb
Host smart-908341c7-9861-4fa3-919e-db7f6ae43df9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240216975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.240216975
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.1943129609
Short name T356
Test name
Test status
Simulation time 37064599 ps
CPU time 1.7 seconds
Started May 30 02:31:31 PM PDT 24
Finished May 30 02:31:35 PM PDT 24
Peak memory 196696 kb
Host smart-8fb1316b-3d5c-4c28-a17d-6a77d4614ff8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943129609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.1943129609
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.2752252037
Short name T671
Test name
Test status
Simulation time 60954260 ps
CPU time 1.53 seconds
Started May 30 02:31:28 PM PDT 24
Finished May 30 02:31:31 PM PDT 24
Peak memory 195904 kb
Host smart-4af63b8d-d5b2-4cec-a0bd-142c6f268b19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752252037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.2752252037
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.602867944
Short name T182
Test name
Test status
Simulation time 128697334 ps
CPU time 1.24 seconds
Started May 30 02:31:31 PM PDT 24
Finished May 30 02:31:34 PM PDT 24
Peak memory 197036 kb
Host smart-dfcb9cb2-b2d5-44a5-821c-0e012e68e55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602867944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.602867944
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.2057649447
Short name T608
Test name
Test status
Simulation time 50585027 ps
CPU time 1.06 seconds
Started May 30 02:31:30 PM PDT 24
Finished May 30 02:31:33 PM PDT 24
Peak memory 196036 kb
Host smart-b46fdd02-3261-445b-b60e-a04749efa2a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057649447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.2057649447
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.2770379062
Short name T627
Test name
Test status
Simulation time 165721222 ps
CPU time 3.85 seconds
Started May 30 02:31:31 PM PDT 24
Finished May 30 02:31:36 PM PDT 24
Peak memory 198044 kb
Host smart-b1b5b2fa-b68b-4ed9-bed8-45766fbda826
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770379062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.2770379062
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.727709126
Short name T383
Test name
Test status
Simulation time 85856783 ps
CPU time 1.08 seconds
Started May 30 02:31:32 PM PDT 24
Finished May 30 02:31:35 PM PDT 24
Peak memory 196432 kb
Host smart-0394f1d9-04c8-42cf-a5f7-e3e643c052ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727709126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.727709126
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.1571631763
Short name T551
Test name
Test status
Simulation time 136447653 ps
CPU time 1.22 seconds
Started May 30 02:31:35 PM PDT 24
Finished May 30 02:31:38 PM PDT 24
Peak memory 194532 kb
Host smart-b3827bf9-bae8-45e8-b8ce-298648c291e2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571631763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.1571631763
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.3431848353
Short name T680
Test name
Test status
Simulation time 9763377081 ps
CPU time 121.56 seconds
Started May 30 02:31:31 PM PDT 24
Finished May 30 02:33:34 PM PDT 24
Peak memory 198160 kb
Host smart-c06cf4ae-401e-42ed-b76d-2d058b0e98b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431848353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.3431848353
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.3475835564
Short name T516
Test name
Test status
Simulation time 265512433660 ps
CPU time 1787.02 seconds
Started May 30 02:31:30 PM PDT 24
Finished May 30 03:01:18 PM PDT 24
Peak memory 198280 kb
Host smart-b4a9ddc1-1e3c-4ed0-8eda-4061eedb6012
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3475835564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.3475835564
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.3071673201
Short name T415
Test name
Test status
Simulation time 14584538 ps
CPU time 0.63 seconds
Started May 30 02:31:35 PM PDT 24
Finished May 30 02:31:37 PM PDT 24
Peak memory 193744 kb
Host smart-7a2f23a3-c1ec-4ac9-8e8e-0d6d44f7187c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071673201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.3071673201
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.1912607011
Short name T368
Test name
Test status
Simulation time 25345135 ps
CPU time 0.78 seconds
Started May 30 02:31:30 PM PDT 24
Finished May 30 02:31:32 PM PDT 24
Peak memory 196072 kb
Host smart-f18c7290-3457-4023-9c53-d91cf4b93e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912607011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.1912607011
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.2417679673
Short name T65
Test name
Test status
Simulation time 2461463029 ps
CPU time 17.69 seconds
Started May 30 02:31:35 PM PDT 24
Finished May 30 02:31:54 PM PDT 24
Peak memory 196152 kb
Host smart-90372418-ae60-44d0-a50b-92e48b95205a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417679673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.2417679673
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.326634004
Short name T342
Test name
Test status
Simulation time 48071331 ps
CPU time 0.69 seconds
Started May 30 02:31:34 PM PDT 24
Finished May 30 02:31:36 PM PDT 24
Peak memory 194872 kb
Host smart-9262156c-eb56-432c-84d2-ef736bea26c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326634004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.326634004
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.358541454
Short name T567
Test name
Test status
Simulation time 652057197 ps
CPU time 0.94 seconds
Started May 30 02:31:27 PM PDT 24
Finished May 30 02:31:28 PM PDT 24
Peak memory 196924 kb
Host smart-fa206823-7815-4bde-b7c0-aab07750b589
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358541454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.358541454
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.3592785922
Short name T259
Test name
Test status
Simulation time 164000129 ps
CPU time 3.21 seconds
Started May 30 02:31:28 PM PDT 24
Finished May 30 02:31:32 PM PDT 24
Peak memory 198172 kb
Host smart-02065968-97f0-4e60-82a6-5c2740165653
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592785922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.3592785922
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.3043277462
Short name T257
Test name
Test status
Simulation time 147798421 ps
CPU time 2.01 seconds
Started May 30 02:31:27 PM PDT 24
Finished May 30 02:31:31 PM PDT 24
Peak memory 198112 kb
Host smart-ae9dc5b4-233f-4c34-bdad-f031ff0d2a33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043277462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.3043277462
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.4082474773
Short name T143
Test name
Test status
Simulation time 130192338 ps
CPU time 1.01 seconds
Started May 30 02:31:32 PM PDT 24
Finished May 30 02:31:35 PM PDT 24
Peak memory 195872 kb
Host smart-bdd8fe9a-b98b-476e-8236-180815d79ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082474773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.4082474773
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.1666815215
Short name T67
Test name
Test status
Simulation time 65134028 ps
CPU time 1.22 seconds
Started May 30 02:31:29 PM PDT 24
Finished May 30 02:31:32 PM PDT 24
Peak memory 196596 kb
Host smart-bd6d0d85-c043-4978-84b5-357749e88eb0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666815215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.1666815215
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3943761708
Short name T509
Test name
Test status
Simulation time 493267616 ps
CPU time 3.61 seconds
Started May 30 02:31:31 PM PDT 24
Finished May 30 02:31:37 PM PDT 24
Peak memory 198076 kb
Host smart-40f41f59-d7d5-4cd4-9c2b-a84d811a8270
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943761708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3943761708
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.3409464428
Short name T408
Test name
Test status
Simulation time 68496769 ps
CPU time 0.87 seconds
Started May 30 02:31:27 PM PDT 24
Finished May 30 02:31:29 PM PDT 24
Peak memory 195484 kb
Host smart-33c9f27f-8c31-4e87-a38a-667fa245d3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409464428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.3409464428
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.3166322091
Short name T519
Test name
Test status
Simulation time 79659479 ps
CPU time 1.28 seconds
Started May 30 02:31:28 PM PDT 24
Finished May 30 02:31:30 PM PDT 24
Peak memory 198108 kb
Host smart-6ffbc702-50b0-448e-b690-90d920e66902
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166322091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.3166322091
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.612947671
Short name T32
Test name
Test status
Simulation time 13998347649 ps
CPU time 172.25 seconds
Started May 30 02:31:34 PM PDT 24
Finished May 30 02:34:28 PM PDT 24
Peak memory 198232 kb
Host smart-d4199c63-2c1f-437c-b3dd-4d0eaa58078c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612947671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.g
pio_stress_all.612947671
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.3774735654
Short name T75
Test name
Test status
Simulation time 53720251010 ps
CPU time 338.17 seconds
Started May 30 02:31:30 PM PDT 24
Finished May 30 02:37:09 PM PDT 24
Peak memory 198320 kb
Host smart-7ed8707a-5d7a-4827-b84a-d65f81ff564e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3774735654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.3774735654
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.3484475441
Short name T60
Test name
Test status
Simulation time 15797606 ps
CPU time 0.57 seconds
Started May 30 02:31:25 PM PDT 24
Finished May 30 02:31:26 PM PDT 24
Peak memory 193980 kb
Host smart-3a2f2919-28cc-4530-9853-4a9f10263d59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484475441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.3484475441
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.220293459
Short name T537
Test name
Test status
Simulation time 62494753 ps
CPU time 0.91 seconds
Started May 30 02:31:28 PM PDT 24
Finished May 30 02:31:30 PM PDT 24
Peak memory 195544 kb
Host smart-a535c101-047e-4379-ba18-7254facfc0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220293459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.220293459
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.2055488856
Short name T444
Test name
Test status
Simulation time 429510169 ps
CPU time 21.03 seconds
Started May 30 02:31:31 PM PDT 24
Finished May 30 02:31:54 PM PDT 24
Peak memory 198060 kb
Host smart-caa4ea41-0cba-485b-b128-c9c367cb83e2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055488856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.2055488856
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.1389425512
Short name T302
Test name
Test status
Simulation time 32670257 ps
CPU time 0.71 seconds
Started May 30 02:31:31 PM PDT 24
Finished May 30 02:31:34 PM PDT 24
Peak memory 194756 kb
Host smart-ae88dfa1-ca79-486c-aa16-4ceae1e17576
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389425512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.1389425512
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.404539000
Short name T686
Test name
Test status
Simulation time 38892867 ps
CPU time 0.67 seconds
Started May 30 02:31:30 PM PDT 24
Finished May 30 02:31:32 PM PDT 24
Peak memory 194308 kb
Host smart-ec8db2db-d38c-4d5c-bf15-5e25759c851a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404539000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.404539000
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.1998324233
Short name T164
Test name
Test status
Simulation time 158810718 ps
CPU time 1.85 seconds
Started May 30 02:31:27 PM PDT 24
Finished May 30 02:31:30 PM PDT 24
Peak memory 198036 kb
Host smart-653fd10d-09e8-4185-ad00-ebdf5731b573
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998324233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.1998324233
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.1209940839
Short name T345
Test name
Test status
Simulation time 151299590 ps
CPU time 1.92 seconds
Started May 30 02:31:27 PM PDT 24
Finished May 30 02:31:30 PM PDT 24
Peak memory 196524 kb
Host smart-1717a0e3-be64-49f5-b554-f8bec513728c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209940839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.1209940839
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.3790019609
Short name T476
Test name
Test status
Simulation time 96744805 ps
CPU time 1.23 seconds
Started May 30 02:31:26 PM PDT 24
Finished May 30 02:31:28 PM PDT 24
Peak memory 198020 kb
Host smart-87c4c923-5e36-4db6-b408-201313909f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790019609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.3790019609
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.721369329
Short name T421
Test name
Test status
Simulation time 34648250 ps
CPU time 1.19 seconds
Started May 30 02:31:27 PM PDT 24
Finished May 30 02:31:29 PM PDT 24
Peak memory 197152 kb
Host smart-b8d0a93f-1be7-43b8-a20a-bcb7021e5f39
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721369329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullup
_pulldown.721369329
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.3387996750
Short name T393
Test name
Test status
Simulation time 96972953 ps
CPU time 2.39 seconds
Started May 30 02:31:28 PM PDT 24
Finished May 30 02:31:32 PM PDT 24
Peak memory 198048 kb
Host smart-22bec03b-7fc0-4547-b887-4f1462e67006
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387996750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.3387996750
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.911624462
Short name T582
Test name
Test status
Simulation time 453113536 ps
CPU time 1.18 seconds
Started May 30 02:31:30 PM PDT 24
Finished May 30 02:31:32 PM PDT 24
Peak memory 195816 kb
Host smart-ff812134-959a-4769-9169-38462fcf3e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911624462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.911624462
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.1811420926
Short name T233
Test name
Test status
Simulation time 36042967 ps
CPU time 1.18 seconds
Started May 30 02:31:25 PM PDT 24
Finished May 30 02:31:27 PM PDT 24
Peak memory 195728 kb
Host smart-b37eb065-6bf3-4328-ba00-08dee7b936c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811420926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.1811420926
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.1207698937
Short name T404
Test name
Test status
Simulation time 12585852383 ps
CPU time 39.62 seconds
Started May 30 02:31:28 PM PDT 24
Finished May 30 02:32:09 PM PDT 24
Peak memory 198240 kb
Host smart-4e547847-0063-49cb-aa1b-e73a453794c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207698937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.1207698937
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.2218737169
Short name T72
Test name
Test status
Simulation time 127724006958 ps
CPU time 1674.97 seconds
Started May 30 02:31:31 PM PDT 24
Finished May 30 02:59:28 PM PDT 24
Peak memory 198276 kb
Host smart-6b47231f-68a6-4da4-9647-2db6039d8a26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2218737169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.2218737169
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.658643848
Short name T503
Test name
Test status
Simulation time 31227398 ps
CPU time 0.62 seconds
Started May 30 02:31:33 PM PDT 24
Finished May 30 02:31:35 PM PDT 24
Peak memory 194964 kb
Host smart-576f14fe-26e5-4078-bd28-6d6df7aff6d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658643848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.658643848
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.4196274998
Short name T183
Test name
Test status
Simulation time 58275266 ps
CPU time 0.63 seconds
Started May 30 02:31:32 PM PDT 24
Finished May 30 02:31:34 PM PDT 24
Peak memory 193920 kb
Host smart-b7d939eb-0c53-4955-bd89-e4b20ac14489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196274998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.4196274998
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.2421480975
Short name T657
Test name
Test status
Simulation time 363469806 ps
CPU time 9.28 seconds
Started May 30 02:31:33 PM PDT 24
Finished May 30 02:31:43 PM PDT 24
Peak memory 198008 kb
Host smart-7e3b4771-070a-453c-9e96-0759edaaf39e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421480975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.2421480975
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.1720228270
Short name T682
Test name
Test status
Simulation time 55806595 ps
CPU time 0.7 seconds
Started May 30 02:31:32 PM PDT 24
Finished May 30 02:31:35 PM PDT 24
Peak memory 194724 kb
Host smart-a545fafa-bae8-4575-9b95-c74eb607edaf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720228270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.1720228270
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.2460749807
Short name T291
Test name
Test status
Simulation time 104772906 ps
CPU time 0.85 seconds
Started May 30 02:31:32 PM PDT 24
Finished May 30 02:31:34 PM PDT 24
Peak memory 196768 kb
Host smart-84df434d-bf2d-4451-ab63-8d1e315c8132
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460749807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.2460749807
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.668676300
Short name T184
Test name
Test status
Simulation time 190031462 ps
CPU time 2.32 seconds
Started May 30 02:31:32 PM PDT 24
Finished May 30 02:31:36 PM PDT 24
Peak memory 196492 kb
Host smart-d315922b-9f85-41ac-8eff-29f7cdbb3dff
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668676300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.gpio_intr_with_filter_rand_intr_event.668676300
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.3201008026
Short name T349
Test name
Test status
Simulation time 3106044897 ps
CPU time 3.42 seconds
Started May 30 02:31:32 PM PDT 24
Finished May 30 02:31:37 PM PDT 24
Peak memory 197212 kb
Host smart-9cbd2119-8b5a-4115-8fbb-0f0b19a274ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201008026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.3201008026
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.1261586910
Short name T719
Test name
Test status
Simulation time 102246076 ps
CPU time 0.74 seconds
Started May 30 02:31:31 PM PDT 24
Finished May 30 02:31:33 PM PDT 24
Peak memory 195476 kb
Host smart-2c8be3e5-9540-4e7b-9815-bab498980eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261586910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.1261586910
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.2208307667
Short name T631
Test name
Test status
Simulation time 58349778 ps
CPU time 1.24 seconds
Started May 30 02:31:32 PM PDT 24
Finished May 30 02:31:35 PM PDT 24
Peak memory 195872 kb
Host smart-cad86c23-0fec-465f-b880-1761ab86cbb1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208307667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.2208307667
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.2412403327
Short name T369
Test name
Test status
Simulation time 1396895665 ps
CPU time 3.46 seconds
Started May 30 02:31:36 PM PDT 24
Finished May 30 02:31:41 PM PDT 24
Peak memory 198064 kb
Host smart-d8dd4ad4-03db-465a-935b-83ac1f958556
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412403327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.2412403327
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.1340107122
Short name T311
Test name
Test status
Simulation time 32849037 ps
CPU time 0.84 seconds
Started May 30 02:31:32 PM PDT 24
Finished May 30 02:31:34 PM PDT 24
Peak memory 196372 kb
Host smart-9deb4aba-991b-4ffc-bf98-4c8ce6ce8bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340107122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.1340107122
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.2782918124
Short name T524
Test name
Test status
Simulation time 161701045 ps
CPU time 1.14 seconds
Started May 30 02:31:35 PM PDT 24
Finished May 30 02:31:38 PM PDT 24
Peak memory 196496 kb
Host smart-976655a5-405b-47dd-961e-85eb8da2b52f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782918124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.2782918124
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.1532035447
Short name T579
Test name
Test status
Simulation time 15341843065 ps
CPU time 191.6 seconds
Started May 30 02:31:29 PM PDT 24
Finished May 30 02:34:42 PM PDT 24
Peak memory 198232 kb
Host smart-6f3d0bd4-00fb-407f-ba80-32e6b93204ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532035447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.1532035447
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.1787561190
Short name T652
Test name
Test status
Simulation time 13378474 ps
CPU time 0.56 seconds
Started May 30 02:30:42 PM PDT 24
Finished May 30 02:30:43 PM PDT 24
Peak memory 193968 kb
Host smart-a18fbcaa-e1cb-42bb-b188-99df944a45c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787561190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.1787561190
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.1071617568
Short name T279
Test name
Test status
Simulation time 68919019 ps
CPU time 0.66 seconds
Started May 30 02:30:47 PM PDT 24
Finished May 30 02:30:50 PM PDT 24
Peak memory 193972 kb
Host smart-ed9514c4-22b3-4e6b-ba3e-1c688d5baeca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071617568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.1071617568
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.2257327510
Short name T427
Test name
Test status
Simulation time 3162505613 ps
CPU time 21.27 seconds
Started May 30 02:30:40 PM PDT 24
Finished May 30 02:31:02 PM PDT 24
Peak memory 196984 kb
Host smart-3d49bc82-88ad-4e4b-a200-4f4352d43431
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257327510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.2257327510
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.4013303720
Short name T697
Test name
Test status
Simulation time 57772168 ps
CPU time 0.92 seconds
Started May 30 02:30:47 PM PDT 24
Finished May 30 02:30:50 PM PDT 24
Peak memory 195968 kb
Host smart-b8780ffd-92b1-4e8c-8181-1f70a55c2d5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013303720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.4013303720
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.961606094
Short name T158
Test name
Test status
Simulation time 75924226 ps
CPU time 0.84 seconds
Started May 30 02:30:41 PM PDT 24
Finished May 30 02:30:43 PM PDT 24
Peak memory 195632 kb
Host smart-b50adc05-c310-42a6-b9d4-0971e3d1955d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961606094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.961606094
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.538893882
Short name T351
Test name
Test status
Simulation time 159912231 ps
CPU time 2.84 seconds
Started May 30 02:30:41 PM PDT 24
Finished May 30 02:30:46 PM PDT 24
Peak memory 198152 kb
Host smart-25826223-d866-48c5-a935-cf4da2a426f5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538893882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.gpio_intr_with_filter_rand_intr_event.538893882
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.253777077
Short name T223
Test name
Test status
Simulation time 216224534 ps
CPU time 3.26 seconds
Started May 30 02:30:47 PM PDT 24
Finished May 30 02:30:52 PM PDT 24
Peak memory 198024 kb
Host smart-864ecbf2-0f2e-48be-a94e-a6e14f74eb97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253777077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.253777077
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.922067362
Short name T465
Test name
Test status
Simulation time 33214761 ps
CPU time 1.26 seconds
Started May 30 02:30:43 PM PDT 24
Finished May 30 02:30:45 PM PDT 24
Peak memory 196992 kb
Host smart-9296e6ce-ba08-4fc1-ba09-daf31abc714c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922067362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.922067362
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.2565375388
Short name T454
Test name
Test status
Simulation time 25394981 ps
CPU time 0.74 seconds
Started May 30 02:30:42 PM PDT 24
Finished May 30 02:30:44 PM PDT 24
Peak memory 195528 kb
Host smart-da5d72c3-7976-432f-9e52-aaab341fea26
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565375388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.2565375388
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.3014509903
Short name T44
Test name
Test status
Simulation time 146256346 ps
CPU time 0.9 seconds
Started May 30 02:30:38 PM PDT 24
Finished May 30 02:30:41 PM PDT 24
Peak memory 213844 kb
Host smart-01373649-778e-4312-b873-4338a315ae28
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014509903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.3014509903
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.3945329553
Short name T478
Test name
Test status
Simulation time 36948545 ps
CPU time 1.11 seconds
Started May 30 02:30:42 PM PDT 24
Finished May 30 02:30:44 PM PDT 24
Peak memory 195564 kb
Host smart-9ee39320-e8ad-4322-a6ae-100bbb05f71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945329553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.3945329553
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.2914458859
Short name T372
Test name
Test status
Simulation time 114034866 ps
CPU time 0.98 seconds
Started May 30 02:30:40 PM PDT 24
Finished May 30 02:30:42 PM PDT 24
Peak memory 196624 kb
Host smart-c92572c3-4bfc-4e4b-b894-cd6593528b8c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914458859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.2914458859
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.3798385467
Short name T254
Test name
Test status
Simulation time 25894497338 ps
CPU time 158.1 seconds
Started May 30 02:30:42 PM PDT 24
Finished May 30 02:33:21 PM PDT 24
Peak memory 198244 kb
Host smart-42680cd9-cd5c-4af7-9df3-db74d5001781
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798385467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.3798385467
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.1291467131
Short name T446
Test name
Test status
Simulation time 181002862181 ps
CPU time 1723.84 seconds
Started May 30 02:30:41 PM PDT 24
Finished May 30 02:59:27 PM PDT 24
Peak memory 198232 kb
Host smart-a0f4a7d3-132f-46b3-a2fe-04bcc18d5289
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1291467131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.1291467131
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.949902765
Short name T422
Test name
Test status
Simulation time 20712841 ps
CPU time 0.61 seconds
Started May 30 02:31:35 PM PDT 24
Finished May 30 02:31:37 PM PDT 24
Peak memory 193896 kb
Host smart-d1def6d3-37ce-48f5-9c3a-feec679fe0ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949902765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.949902765
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.3700989721
Short name T403
Test name
Test status
Simulation time 30324877 ps
CPU time 0.87 seconds
Started May 30 02:31:34 PM PDT 24
Finished May 30 02:31:36 PM PDT 24
Peak memory 196648 kb
Host smart-896e417e-7686-4818-910a-abd4a0c1ddb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700989721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.3700989721
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.2085531874
Short name T423
Test name
Test status
Simulation time 3270388277 ps
CPU time 17.25 seconds
Started May 30 02:31:28 PM PDT 24
Finished May 30 02:31:46 PM PDT 24
Peak memory 196848 kb
Host smart-20c26d13-0ca7-4b2e-a652-5a761f99077e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085531874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.2085531874
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.814023442
Short name T290
Test name
Test status
Simulation time 50232134 ps
CPU time 0.82 seconds
Started May 30 02:31:36 PM PDT 24
Finished May 30 02:31:38 PM PDT 24
Peak memory 196820 kb
Host smart-fa40e032-bfc1-4a4c-b349-569212a49588
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814023442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.814023442
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.4116621092
Short name T564
Test name
Test status
Simulation time 26765113 ps
CPU time 0.89 seconds
Started May 30 02:31:34 PM PDT 24
Finished May 30 02:31:37 PM PDT 24
Peak memory 196588 kb
Host smart-4dfc8e8e-7d9a-495d-9ce7-2a69ae91ddb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116621092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.4116621092
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.3790098818
Short name T477
Test name
Test status
Simulation time 359077406 ps
CPU time 2.21 seconds
Started May 30 02:31:36 PM PDT 24
Finished May 30 02:31:40 PM PDT 24
Peak memory 196544 kb
Host smart-b7f3d737-20da-4353-914b-e7fe88c1d049
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790098818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.3790098818
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.3688187247
Short name T489
Test name
Test status
Simulation time 102225540 ps
CPU time 2.7 seconds
Started May 30 02:31:35 PM PDT 24
Finished May 30 02:31:39 PM PDT 24
Peak memory 196964 kb
Host smart-1318bc8c-ce18-4974-ba58-ab834f2bd16d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688187247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.3688187247
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.1453194445
Short name T520
Test name
Test status
Simulation time 170948819 ps
CPU time 0.94 seconds
Started May 30 02:31:34 PM PDT 24
Finished May 30 02:31:37 PM PDT 24
Peak memory 197488 kb
Host smart-c4d1f1bb-03a9-49ad-908c-f0040fe78e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453194445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.1453194445
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.1001297122
Short name T300
Test name
Test status
Simulation time 57531184 ps
CPU time 1.39 seconds
Started May 30 02:31:36 PM PDT 24
Finished May 30 02:31:39 PM PDT 24
Peak memory 196668 kb
Host smart-79c2391b-9b36-46b8-a975-1ceaa4c1d59a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001297122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.1001297122
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.961899845
Short name T5
Test name
Test status
Simulation time 377314323 ps
CPU time 4.58 seconds
Started May 30 02:31:36 PM PDT 24
Finished May 30 02:31:42 PM PDT 24
Peak memory 198040 kb
Host smart-ed210290-a764-42ae-b518-5c8d8304c9a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961899845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ran
dom_long_reg_writes_reg_reads.961899845
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.1704016323
Short name T655
Test name
Test status
Simulation time 58523058 ps
CPU time 1.11 seconds
Started May 30 02:31:32 PM PDT 24
Finished May 30 02:31:34 PM PDT 24
Peak memory 195880 kb
Host smart-7514a7c3-7721-493a-b6ee-0f5d13ba791c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704016323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.1704016323
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.775559202
Short name T244
Test name
Test status
Simulation time 99922115 ps
CPU time 1.43 seconds
Started May 30 02:31:28 PM PDT 24
Finished May 30 02:31:31 PM PDT 24
Peak memory 196732 kb
Host smart-a97f51d6-38ca-4c21-9db3-788592740d2b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775559202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.775559202
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.1845261867
Short name T112
Test name
Test status
Simulation time 19737593606 ps
CPU time 124.79 seconds
Started May 30 02:31:35 PM PDT 24
Finished May 30 02:33:41 PM PDT 24
Peak memory 198220 kb
Host smart-ce770205-b79c-4172-8184-f2e1f2d5957a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845261867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.1845261867
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.2937903217
Short name T310
Test name
Test status
Simulation time 30456821 ps
CPU time 0.56 seconds
Started May 30 02:31:32 PM PDT 24
Finished May 30 02:31:34 PM PDT 24
Peak memory 193940 kb
Host smart-d7d94778-7f4c-49a8-a4fa-f3ee59e7161c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937903217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.2937903217
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.3307360721
Short name T715
Test name
Test status
Simulation time 91436718 ps
CPU time 0.98 seconds
Started May 30 02:31:35 PM PDT 24
Finished May 30 02:31:37 PM PDT 24
Peak memory 196628 kb
Host smart-a0a43307-db62-406a-b03e-5c14ab6da2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307360721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.3307360721
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.3487111983
Short name T16
Test name
Test status
Simulation time 482055134 ps
CPU time 17.01 seconds
Started May 30 02:31:30 PM PDT 24
Finished May 30 02:31:48 PM PDT 24
Peak memory 196844 kb
Host smart-41fa59b9-58ba-448d-9a92-d821e51375db
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487111983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.3487111983
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.648743125
Short name T2
Test name
Test status
Simulation time 223929326 ps
CPU time 0.83 seconds
Started May 30 02:31:34 PM PDT 24
Finished May 30 02:31:37 PM PDT 24
Peak memory 195796 kb
Host smart-f42999cd-422d-4675-b787-b780debc3fba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648743125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.648743125
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.293923496
Short name T380
Test name
Test status
Simulation time 336079386 ps
CPU time 1.41 seconds
Started May 30 02:31:19 PM PDT 24
Finished May 30 02:31:22 PM PDT 24
Peak memory 196064 kb
Host smart-7f9816d5-2784-4ea1-97ac-f36bc69e1190
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293923496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.293923496
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.302082231
Short name T442
Test name
Test status
Simulation time 68180579 ps
CPU time 2.88 seconds
Started May 30 02:31:32 PM PDT 24
Finished May 30 02:31:37 PM PDT 24
Peak memory 198056 kb
Host smart-e9f2345b-6c00-473a-8cb1-beb8e8e19ee1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302082231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.gpio_intr_with_filter_rand_intr_event.302082231
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.1323257483
Short name T485
Test name
Test status
Simulation time 969978382 ps
CPU time 2.85 seconds
Started May 30 02:31:30 PM PDT 24
Finished May 30 02:31:34 PM PDT 24
Peak memory 198068 kb
Host smart-e0f538f4-f8f6-490c-a5f2-1dfb7009f4f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323257483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.1323257483
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.4217678774
Short name T482
Test name
Test status
Simulation time 68332668 ps
CPU time 0.7 seconds
Started May 30 02:31:36 PM PDT 24
Finished May 30 02:31:38 PM PDT 24
Peak memory 194540 kb
Host smart-bafc7158-95f9-4d24-801b-77bed462ff3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217678774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.4217678774
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.2527335095
Short name T573
Test name
Test status
Simulation time 20371995 ps
CPU time 0.73 seconds
Started May 30 02:31:49 PM PDT 24
Finished May 30 02:31:52 PM PDT 24
Peak memory 195632 kb
Host smart-369bea0e-64d1-4044-aa2c-309a8bd8a030
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527335095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.2527335095
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.2034716365
Short name T265
Test name
Test status
Simulation time 280548304 ps
CPU time 4.75 seconds
Started May 30 02:31:31 PM PDT 24
Finished May 30 02:31:38 PM PDT 24
Peak memory 197896 kb
Host smart-aa696f01-f952-4566-94a9-8cb9cdea7414
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034716365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.2034716365
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.2335206076
Short name T397
Test name
Test status
Simulation time 273118951 ps
CPU time 1.39 seconds
Started May 30 02:31:34 PM PDT 24
Finished May 30 02:31:37 PM PDT 24
Peak memory 196784 kb
Host smart-ef69b633-02b3-4e43-babb-a52d11f106e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335206076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.2335206076
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.1456289770
Short name T420
Test name
Test status
Simulation time 52130826 ps
CPU time 0.93 seconds
Started May 30 02:31:35 PM PDT 24
Finished May 30 02:31:38 PM PDT 24
Peak memory 194540 kb
Host smart-90da13eb-c35e-4cd4-8a3d-8a30bb58a45c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456289770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.1456289770
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.826099982
Short name T703
Test name
Test status
Simulation time 27751624418 ps
CPU time 179.26 seconds
Started May 30 02:31:31 PM PDT 24
Finished May 30 02:34:32 PM PDT 24
Peak memory 198212 kb
Host smart-00f72c33-113a-4dfb-8997-af0557567054
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826099982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.g
pio_stress_all.826099982
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.1978509852
Short name T73
Test name
Test status
Simulation time 272128236132 ps
CPU time 1402.45 seconds
Started May 30 02:31:31 PM PDT 24
Finished May 30 02:54:55 PM PDT 24
Peak memory 198288 kb
Host smart-a0890962-ce30-440e-b885-d6537237aeb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1978509852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.1978509852
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.3528882473
Short name T46
Test name
Test status
Simulation time 44876154 ps
CPU time 0.58 seconds
Started May 30 02:31:52 PM PDT 24
Finished May 30 02:31:54 PM PDT 24
Peak memory 194152 kb
Host smart-19183649-d2d1-4102-a428-31e75cf58490
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528882473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.3528882473
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.2569691340
Short name T31
Test name
Test status
Simulation time 123368343 ps
CPU time 0.86 seconds
Started May 30 02:31:43 PM PDT 24
Finished May 30 02:31:46 PM PDT 24
Peak memory 195548 kb
Host smart-0921201a-2e85-422d-9dbd-609cd4445ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569691340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.2569691340
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.1142986141
Short name T600
Test name
Test status
Simulation time 1480997272 ps
CPU time 25.59 seconds
Started May 30 02:31:43 PM PDT 24
Finished May 30 02:32:11 PM PDT 24
Peak memory 198056 kb
Host smart-2c13aa90-9e08-4faa-94ad-a9c14f63e86e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142986141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.1142986141
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.1787940148
Short name T159
Test name
Test status
Simulation time 58002399 ps
CPU time 0.82 seconds
Started May 30 02:31:47 PM PDT 24
Finished May 30 02:31:50 PM PDT 24
Peak memory 196820 kb
Host smart-bddbf39f-e30c-4f16-a0ce-bf5b827f95c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787940148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.1787940148
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.3749244000
Short name T193
Test name
Test status
Simulation time 54864794 ps
CPU time 1.03 seconds
Started May 30 02:31:46 PM PDT 24
Finished May 30 02:31:49 PM PDT 24
Peak memory 196716 kb
Host smart-05e486a2-0109-4a27-9786-c2dc5084b33a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749244000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.3749244000
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.1150891508
Short name T484
Test name
Test status
Simulation time 63358585 ps
CPU time 2.37 seconds
Started May 30 02:31:46 PM PDT 24
Finished May 30 02:31:51 PM PDT 24
Peak memory 198108 kb
Host smart-8474cb67-2d60-470b-9ce6-9ecc672d7937
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150891508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.1150891508
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.3579163107
Short name T189
Test name
Test status
Simulation time 761919121 ps
CPU time 3.23 seconds
Started May 30 02:31:42 PM PDT 24
Finished May 30 02:31:46 PM PDT 24
Peak memory 198044 kb
Host smart-bfd1b973-aabc-4b0d-a049-2585666de3d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579163107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.3579163107
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.1085432860
Short name T169
Test name
Test status
Simulation time 23963039 ps
CPU time 0.96 seconds
Started May 30 02:31:43 PM PDT 24
Finished May 30 02:31:46 PM PDT 24
Peak memory 196012 kb
Host smart-8faf30b7-a300-4f80-8791-b280ec1ab9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085432860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.1085432860
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.431587094
Short name T210
Test name
Test status
Simulation time 280954234 ps
CPU time 0.97 seconds
Started May 30 02:31:41 PM PDT 24
Finished May 30 02:31:43 PM PDT 24
Peak memory 195920 kb
Host smart-770b9d8c-8170-43e3-b6d3-866a2425b1da
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431587094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullup
_pulldown.431587094
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.150698324
Short name T7
Test name
Test status
Simulation time 208719408 ps
CPU time 2.88 seconds
Started May 30 02:31:45 PM PDT 24
Finished May 30 02:31:51 PM PDT 24
Peak memory 198100 kb
Host smart-5b724fdb-338b-4bfa-9eee-161587bcb00e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150698324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ran
dom_long_reg_writes_reg_reads.150698324
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.2629166220
Short name T270
Test name
Test status
Simulation time 72202483 ps
CPU time 1.1 seconds
Started May 30 02:31:32 PM PDT 24
Finished May 30 02:31:35 PM PDT 24
Peak memory 195804 kb
Host smart-2f3f221a-110e-4be1-8662-95e7af9c3f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629166220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.2629166220
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.642248437
Short name T511
Test name
Test status
Simulation time 70891948 ps
CPU time 1.01 seconds
Started May 30 02:31:34 PM PDT 24
Finished May 30 02:31:37 PM PDT 24
Peak memory 195832 kb
Host smart-f3f70749-752d-4f00-8b55-ed90928933de
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642248437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.642248437
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.1649348554
Short name T526
Test name
Test status
Simulation time 42864609344 ps
CPU time 146.5 seconds
Started May 30 02:31:42 PM PDT 24
Finished May 30 02:34:09 PM PDT 24
Peak memory 198216 kb
Host smart-4eb76959-a603-467a-a41f-fb4ddff4736e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649348554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.1649348554
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.2302940840
Short name T514
Test name
Test status
Simulation time 38033706 ps
CPU time 0.95 seconds
Started May 30 02:31:46 PM PDT 24
Finished May 30 02:31:49 PM PDT 24
Peak memory 196592 kb
Host smart-8c1ecae3-eae9-4073-b8cc-c8dd01a2d923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302940840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.2302940840
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.2733449860
Short name T248
Test name
Test status
Simulation time 157061351 ps
CPU time 8.63 seconds
Started May 30 02:31:46 PM PDT 24
Finished May 30 02:31:57 PM PDT 24
Peak memory 197972 kb
Host smart-e0d4c465-e1df-442c-b647-a9b4b1663e78
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733449860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.2733449860
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.3694060102
Short name T157
Test name
Test status
Simulation time 315334417 ps
CPU time 1.1 seconds
Started May 30 02:31:42 PM PDT 24
Finished May 30 02:31:44 PM PDT 24
Peak memory 197780 kb
Host smart-c2a1e022-c140-4f9a-83b5-79874f4e3125
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694060102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3694060102
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.685267141
Short name T440
Test name
Test status
Simulation time 134050740 ps
CPU time 1.19 seconds
Started May 30 02:31:47 PM PDT 24
Finished May 30 02:31:51 PM PDT 24
Peak memory 196456 kb
Host smart-c34013b2-a493-4379-983e-d170eccffc1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685267141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.685267141
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.3158364675
Short name T416
Test name
Test status
Simulation time 46604408 ps
CPU time 1.59 seconds
Started May 30 02:31:48 PM PDT 24
Finished May 30 02:31:52 PM PDT 24
Peak memory 196676 kb
Host smart-b06cefa3-a723-4316-b37c-66889f226e3a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158364675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.3158364675
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.1144780754
Short name T606
Test name
Test status
Simulation time 139914234 ps
CPU time 1.88 seconds
Started May 30 02:31:44 PM PDT 24
Finished May 30 02:31:49 PM PDT 24
Peak memory 196168 kb
Host smart-b98ddd2f-1fc3-4ce8-9c44-aa6bfcb11854
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144780754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.1144780754
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.761709050
Short name T487
Test name
Test status
Simulation time 463980835 ps
CPU time 0.95 seconds
Started May 30 02:31:45 PM PDT 24
Finished May 30 02:31:49 PM PDT 24
Peak memory 196628 kb
Host smart-4ec63af9-0fce-4275-b935-5e8815fc39d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761709050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.761709050
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.1556409639
Short name T214
Test name
Test status
Simulation time 117667222 ps
CPU time 0.85 seconds
Started May 30 02:31:46 PM PDT 24
Finished May 30 02:31:49 PM PDT 24
Peak memory 196440 kb
Host smart-b6dc1e6a-26b7-4f42-b270-36393ce45e98
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556409639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.1556409639
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.768137747
Short name T196
Test name
Test status
Simulation time 1113457528 ps
CPU time 4.71 seconds
Started May 30 02:31:46 PM PDT 24
Finished May 30 02:31:53 PM PDT 24
Peak memory 198068 kb
Host smart-de8d107c-e058-4b0d-9bd2-094c32719b46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768137747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ran
dom_long_reg_writes_reg_reads.768137747
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.2466134385
Short name T273
Test name
Test status
Simulation time 244900137 ps
CPU time 1.36 seconds
Started May 30 02:31:52 PM PDT 24
Finished May 30 02:31:55 PM PDT 24
Peak memory 196524 kb
Host smart-12a7f6c8-b992-455d-b58f-95a93fb462c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466134385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.2466134385
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.767176326
Short name T218
Test name
Test status
Simulation time 58583956 ps
CPU time 1.21 seconds
Started May 30 02:31:44 PM PDT 24
Finished May 30 02:31:48 PM PDT 24
Peak memory 195932 kb
Host smart-1788c7db-dec7-4f91-a11a-87f8a67e62bf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767176326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.767176326
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.713924338
Short name T375
Test name
Test status
Simulation time 41266131159 ps
CPU time 65.8 seconds
Started May 30 02:31:43 PM PDT 24
Finished May 30 02:32:51 PM PDT 24
Peak memory 198252 kb
Host smart-0d30ee11-6dc6-4418-9dde-2539c607f1a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713924338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.g
pio_stress_all.713924338
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.3817997708
Short name T700
Test name
Test status
Simulation time 13697261 ps
CPU time 0.67 seconds
Started May 30 02:31:45 PM PDT 24
Finished May 30 02:31:48 PM PDT 24
Peak memory 194604 kb
Host smart-6fcf491d-d3d2-4bd5-a001-8453d004d490
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817997708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.3817997708
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.2765428172
Short name T548
Test name
Test status
Simulation time 29533193 ps
CPU time 0.61 seconds
Started May 30 02:31:47 PM PDT 24
Finished May 30 02:31:51 PM PDT 24
Peak memory 194756 kb
Host smart-23074907-7dcf-4357-8603-bc1931b3d1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765428172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.2765428172
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.2824273876
Short name T374
Test name
Test status
Simulation time 1693622502 ps
CPU time 13.61 seconds
Started May 30 02:31:42 PM PDT 24
Finished May 30 02:31:57 PM PDT 24
Peak memory 195524 kb
Host smart-ecbe52a3-ddc6-4550-9331-cefa59097f2a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824273876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.2824273876
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.130471360
Short name T452
Test name
Test status
Simulation time 130712094 ps
CPU time 1.01 seconds
Started May 30 02:31:47 PM PDT 24
Finished May 30 02:31:50 PM PDT 24
Peak memory 196720 kb
Host smart-d9fe82f1-1e08-41fc-92d0-2b43bfc361c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130471360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.130471360
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.534934215
Short name T583
Test name
Test status
Simulation time 54225249 ps
CPU time 0.65 seconds
Started May 30 02:31:42 PM PDT 24
Finished May 30 02:31:44 PM PDT 24
Peak memory 195184 kb
Host smart-d5f6bb8c-ff76-434b-a54f-e912a343378b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534934215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.534934215
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.2332847870
Short name T34
Test name
Test status
Simulation time 70835149 ps
CPU time 1.38 seconds
Started May 30 02:31:47 PM PDT 24
Finished May 30 02:31:51 PM PDT 24
Peak memory 196364 kb
Host smart-00c4eba1-67fb-4baa-ace5-e3fcb46092dd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332847870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.2332847870
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.3316309774
Short name T238
Test name
Test status
Simulation time 282919070 ps
CPU time 3.17 seconds
Started May 30 02:31:52 PM PDT 24
Finished May 30 02:31:57 PM PDT 24
Peak memory 195900 kb
Host smart-645a77a6-4077-4e48-9e32-140a193dc65d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316309774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.3316309774
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.3744270532
Short name T523
Test name
Test status
Simulation time 34073091 ps
CPU time 1.17 seconds
Started May 30 02:31:43 PM PDT 24
Finished May 30 02:31:46 PM PDT 24
Peak memory 195932 kb
Host smart-320159d3-7a50-40e8-8986-c9453d7cfc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744270532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.3744270532
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.1923437123
Short name T391
Test name
Test status
Simulation time 62291310 ps
CPU time 1.32 seconds
Started May 30 02:31:47 PM PDT 24
Finished May 30 02:31:51 PM PDT 24
Peak memory 196576 kb
Host smart-3853c363-319c-47e1-b268-e369b55cd5e7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923437123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.1923437123
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.1967837418
Short name T10
Test name
Test status
Simulation time 648499540 ps
CPU time 4.62 seconds
Started May 30 02:31:48 PM PDT 24
Finished May 30 02:31:55 PM PDT 24
Peak memory 198000 kb
Host smart-6cba6ad3-28cf-4a05-97ec-ec8d2af6393e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967837418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.1967837418
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.617673896
Short name T575
Test name
Test status
Simulation time 99962622 ps
CPU time 1.44 seconds
Started May 30 02:31:53 PM PDT 24
Finished May 30 02:31:56 PM PDT 24
Peak memory 196236 kb
Host smart-f62ed587-1c6b-40a0-a21b-4ccc97ee24c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617673896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.617673896
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.29743325
Short name T272
Test name
Test status
Simulation time 238706459 ps
CPU time 1.2 seconds
Started May 30 02:31:46 PM PDT 24
Finished May 30 02:31:50 PM PDT 24
Peak memory 195552 kb
Host smart-5e45d412-c0c3-44b4-85ca-1e1b2d2bbd3a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29743325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.29743325
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.3512625489
Short name T6
Test name
Test status
Simulation time 4106426428 ps
CPU time 43.1 seconds
Started May 30 02:31:46 PM PDT 24
Finished May 30 02:32:32 PM PDT 24
Peak memory 198212 kb
Host smart-4edd4a3d-6fbf-494d-8e88-c4278245a770
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512625489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.3512625489
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.2982218084
Short name T188
Test name
Test status
Simulation time 14203898 ps
CPU time 0.59 seconds
Started May 30 02:31:52 PM PDT 24
Finished May 30 02:31:55 PM PDT 24
Peak memory 193908 kb
Host smart-fcac5543-5d8e-4129-992f-42b0cb91d363
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982218084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.2982218084
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.2772494491
Short name T569
Test name
Test status
Simulation time 224940676 ps
CPU time 0.79 seconds
Started May 30 02:31:45 PM PDT 24
Finished May 30 02:31:49 PM PDT 24
Peak memory 195356 kb
Host smart-d66e47d4-639d-4189-9520-eb6fa307422e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772494491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.2772494491
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.2701228578
Short name T362
Test name
Test status
Simulation time 1000466734 ps
CPU time 19.63 seconds
Started May 30 02:31:48 PM PDT 24
Finished May 30 02:32:10 PM PDT 24
Peak memory 197980 kb
Host smart-9d6c259f-eecf-432a-b6d4-c4b587621a40
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701228578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.2701228578
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.1279820210
Short name T508
Test name
Test status
Simulation time 63154922 ps
CPU time 0.91 seconds
Started May 30 02:31:47 PM PDT 24
Finished May 30 02:31:50 PM PDT 24
Peak memory 196156 kb
Host smart-dd04a198-4c5f-4699-8f04-5e7c32b1b0af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279820210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.1279820210
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.3153553319
Short name T702
Test name
Test status
Simulation time 46606320 ps
CPU time 1.31 seconds
Started May 30 02:31:45 PM PDT 24
Finished May 30 02:31:49 PM PDT 24
Peak memory 196176 kb
Host smart-bc81607f-f8d0-4402-b8db-c6049e5133e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153553319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.3153553319
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.2645470489
Short name T249
Test name
Test status
Simulation time 97875369 ps
CPU time 3.56 seconds
Started May 30 02:31:53 PM PDT 24
Finished May 30 02:31:58 PM PDT 24
Peak memory 197448 kb
Host smart-e6352b4a-4e7b-4541-a7f2-7099e805123a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645470489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.2645470489
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.3766330850
Short name T441
Test name
Test status
Simulation time 52207317 ps
CPU time 1.75 seconds
Started May 30 02:31:45 PM PDT 24
Finished May 30 02:31:50 PM PDT 24
Peak memory 195796 kb
Host smart-92366013-df07-46db-bfe4-0307bab58e18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766330850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.3766330850
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.945832446
Short name T25
Test name
Test status
Simulation time 49445993 ps
CPU time 1.09 seconds
Started May 30 02:31:47 PM PDT 24
Finished May 30 02:31:51 PM PDT 24
Peak memory 196496 kb
Host smart-9feb4943-8758-49a3-b8f2-190ae02bd68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945832446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.945832446
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.1128557586
Short name T616
Test name
Test status
Simulation time 44877935 ps
CPU time 1 seconds
Started May 30 02:31:52 PM PDT 24
Finished May 30 02:31:55 PM PDT 24
Peak memory 195832 kb
Host smart-0c6123b4-8bc5-4e3b-b5a9-9dc22c138b76
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128557586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.1128557586
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.432552665
Short name T418
Test name
Test status
Simulation time 1682321274 ps
CPU time 5.54 seconds
Started May 30 02:31:46 PM PDT 24
Finished May 30 02:31:54 PM PDT 24
Peak memory 198060 kb
Host smart-98db0617-f4b5-41ef-8509-57109cf16a53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432552665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ran
dom_long_reg_writes_reg_reads.432552665
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.1654734120
Short name T156
Test name
Test status
Simulation time 75116193 ps
CPU time 1.21 seconds
Started May 30 02:31:48 PM PDT 24
Finished May 30 02:31:51 PM PDT 24
Peak memory 196904 kb
Host smart-56ae51e8-305b-4852-b8cd-89405aa92566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654734120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.1654734120
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.3821421710
Short name T557
Test name
Test status
Simulation time 89173720 ps
CPU time 1.07 seconds
Started May 30 02:31:44 PM PDT 24
Finished May 30 02:31:47 PM PDT 24
Peak memory 195752 kb
Host smart-893c6e5a-e480-417e-aa44-2c022b9a1a8d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821421710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.3821421710
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.649702456
Short name T198
Test name
Test status
Simulation time 7467940351 ps
CPU time 187.65 seconds
Started May 30 02:31:47 PM PDT 24
Finished May 30 02:34:57 PM PDT 24
Peak memory 198176 kb
Host smart-a2d7a385-0b04-4392-90db-f1a4f72ce42c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649702456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.g
pio_stress_all.649702456
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.3872972497
Short name T296
Test name
Test status
Simulation time 46116574 ps
CPU time 0.57 seconds
Started May 30 02:31:44 PM PDT 24
Finished May 30 02:31:46 PM PDT 24
Peak memory 193920 kb
Host smart-155d6f6c-a7eb-4ae1-97fd-07d514c9e619
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872972497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.3872972497
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.2525995824
Short name T486
Test name
Test status
Simulation time 109501288 ps
CPU time 0.65 seconds
Started May 30 02:31:45 PM PDT 24
Finished May 30 02:31:48 PM PDT 24
Peak memory 194132 kb
Host smart-0bf5ccd0-8386-4207-b0a0-eac7e146e2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525995824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.2525995824
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.1498093397
Short name T306
Test name
Test status
Simulation time 747630135 ps
CPU time 14.04 seconds
Started May 30 02:31:52 PM PDT 24
Finished May 30 02:32:07 PM PDT 24
Peak memory 195528 kb
Host smart-c34cb663-1d0b-44b5-9ea4-ec5831e08b0b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498093397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.1498093397
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.758207416
Short name T126
Test name
Test status
Simulation time 116786799 ps
CPU time 0.95 seconds
Started May 30 02:31:48 PM PDT 24
Finished May 30 02:31:51 PM PDT 24
Peak memory 197032 kb
Host smart-ae4b958c-f263-4f05-a0af-e77bbcfda0b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758207416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.758207416
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.227801056
Short name T212
Test name
Test status
Simulation time 42061522 ps
CPU time 1.23 seconds
Started May 30 02:31:53 PM PDT 24
Finished May 30 02:31:56 PM PDT 24
Peak memory 196744 kb
Host smart-6697317d-2ebc-47c9-b3f1-5bc91feca227
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227801056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.227801056
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.4091622445
Short name T226
Test name
Test status
Simulation time 69828145 ps
CPU time 2.78 seconds
Started May 30 02:31:51 PM PDT 24
Finished May 30 02:31:55 PM PDT 24
Peak memory 198020 kb
Host smart-569bba6b-bcb7-4bc9-8936-51698c390dff
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091622445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.4091622445
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.996253191
Short name T660
Test name
Test status
Simulation time 56331853 ps
CPU time 1.51 seconds
Started May 30 02:31:48 PM PDT 24
Finished May 30 02:31:52 PM PDT 24
Peak memory 196728 kb
Host smart-fe0b0064-0aac-4b40-9bf3-3d354ca3cb9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996253191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger.
996253191
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.482884300
Short name T247
Test name
Test status
Simulation time 105203833 ps
CPU time 0.68 seconds
Started May 30 02:31:52 PM PDT 24
Finished May 30 02:31:54 PM PDT 24
Peak memory 195464 kb
Host smart-2ca23260-86f8-4bc1-9256-1ea008931c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482884300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.482884300
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.3482471357
Short name T330
Test name
Test status
Simulation time 18751996 ps
CPU time 0.77 seconds
Started May 30 02:31:52 PM PDT 24
Finished May 30 02:31:54 PM PDT 24
Peak memory 195556 kb
Host smart-27f7fc3c-b921-419a-9a42-7c417df15d3a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482471357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.3482471357
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1768341447
Short name T670
Test name
Test status
Simulation time 198794462 ps
CPU time 1.13 seconds
Started May 30 02:31:50 PM PDT 24
Finished May 30 02:31:53 PM PDT 24
Peak memory 198008 kb
Host smart-f1ba7fbe-7580-4340-96e1-4a7abf922ae3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768341447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.1768341447
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.2827839927
Short name T191
Test name
Test status
Simulation time 91594477 ps
CPU time 1.3 seconds
Started May 30 02:31:47 PM PDT 24
Finished May 30 02:31:51 PM PDT 24
Peak memory 196604 kb
Host smart-d292020c-a35d-4cf2-88f0-6b633352f532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827839927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.2827839927
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.562554956
Short name T172
Test name
Test status
Simulation time 21064530 ps
CPU time 0.73 seconds
Started May 30 02:31:47 PM PDT 24
Finished May 30 02:31:50 PM PDT 24
Peak memory 194908 kb
Host smart-4df5cc08-b208-42c7-8e3a-c1aec3670c3b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562554956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.562554956
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.4282858926
Short name T396
Test name
Test status
Simulation time 23797422392 ps
CPU time 163.32 seconds
Started May 30 02:31:51 PM PDT 24
Finished May 30 02:34:35 PM PDT 24
Peak memory 198200 kb
Host smart-ffa894f9-afa0-4eaa-a559-041dbe72179b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282858926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.4282858926
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.3012002060
Short name T76
Test name
Test status
Simulation time 39565715323 ps
CPU time 523.57 seconds
Started May 30 02:31:52 PM PDT 24
Finished May 30 02:40:37 PM PDT 24
Peak memory 198236 kb
Host smart-086b6906-020a-4950-b249-e7ce8d907349
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3012002060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.3012002060
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.610680038
Short name T480
Test name
Test status
Simulation time 36389131 ps
CPU time 0.67 seconds
Started May 30 02:31:57 PM PDT 24
Finished May 30 02:32:00 PM PDT 24
Peak memory 194628 kb
Host smart-28ea4a9c-4379-42dc-b2ed-7d6fed6599c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610680038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.610680038
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.4087163533
Short name T12
Test name
Test status
Simulation time 22215205 ps
CPU time 0.63 seconds
Started May 30 02:31:53 PM PDT 24
Finished May 30 02:31:55 PM PDT 24
Peak memory 194072 kb
Host smart-48f411fd-ae7f-43fe-937f-99972174f4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087163533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.4087163533
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.711465625
Short name T540
Test name
Test status
Simulation time 378612386 ps
CPU time 7.17 seconds
Started May 30 02:31:52 PM PDT 24
Finished May 30 02:32:01 PM PDT 24
Peak memory 196968 kb
Host smart-df71b442-1549-4f87-bf11-78ef276afbe2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711465625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stres
s.711465625
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.578638606
Short name T309
Test name
Test status
Simulation time 221162889 ps
CPU time 0.88 seconds
Started May 30 02:31:56 PM PDT 24
Finished May 30 02:31:59 PM PDT 24
Peak memory 196156 kb
Host smart-43c46362-80c5-454c-accb-c2b72130ceb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578638606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.578638606
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.1741438121
Short name T622
Test name
Test status
Simulation time 87356607 ps
CPU time 1.12 seconds
Started May 30 02:31:53 PM PDT 24
Finished May 30 02:31:56 PM PDT 24
Peak memory 196052 kb
Host smart-f81d9677-2e85-47ff-b7b4-7cf3f621c51e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741438121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.1741438121
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.2119155193
Short name T648
Test name
Test status
Simulation time 88319782 ps
CPU time 3.4 seconds
Started May 30 02:31:52 PM PDT 24
Finished May 30 02:31:58 PM PDT 24
Peak memory 198140 kb
Host smart-60bf8fdc-422a-428d-872c-a014e28f2116
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119155193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.2119155193
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.2714664961
Short name T641
Test name
Test status
Simulation time 871963399 ps
CPU time 3.32 seconds
Started May 30 02:31:58 PM PDT 24
Finished May 30 02:32:04 PM PDT 24
Peak memory 198116 kb
Host smart-baff7a4f-e362-4605-8c02-ccfb815336df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714664961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.2714664961
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.1834216993
Short name T586
Test name
Test status
Simulation time 32232951 ps
CPU time 1.27 seconds
Started May 30 02:31:52 PM PDT 24
Finished May 30 02:31:55 PM PDT 24
Peak memory 195864 kb
Host smart-e8ce0cfa-0f05-4a39-ae78-e86496dfd626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834216993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.1834216993
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.1472869672
Short name T284
Test name
Test status
Simulation time 19822032 ps
CPU time 0.75 seconds
Started May 30 02:31:50 PM PDT 24
Finished May 30 02:31:53 PM PDT 24
Peak memory 195040 kb
Host smart-22301ac3-569d-4f30-aa15-6faf71e96e5c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472869672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.1472869672
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.2783381303
Short name T599
Test name
Test status
Simulation time 440635603 ps
CPU time 5.73 seconds
Started May 30 02:31:57 PM PDT 24
Finished May 30 02:32:05 PM PDT 24
Peak memory 198000 kb
Host smart-3a63da2a-a8da-4562-aba4-402ec6c05f2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783381303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.2783381303
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.2245437578
Short name T170
Test name
Test status
Simulation time 415095031 ps
CPU time 1.2 seconds
Started May 30 02:31:52 PM PDT 24
Finished May 30 02:31:56 PM PDT 24
Peak memory 196372 kb
Host smart-562f1aba-ff08-446c-bf06-497000175725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245437578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.2245437578
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.4191638813
Short name T227
Test name
Test status
Simulation time 28203261 ps
CPU time 0.95 seconds
Started May 30 02:31:53 PM PDT 24
Finished May 30 02:31:56 PM PDT 24
Peak memory 196476 kb
Host smart-56a3e0b2-6945-44b0-b8ef-a08033799a20
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191638813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.4191638813
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.44035315
Short name T405
Test name
Test status
Simulation time 5593706944 ps
CPU time 77.77 seconds
Started May 30 02:31:56 PM PDT 24
Finished May 30 02:33:15 PM PDT 24
Peak memory 198224 kb
Host smart-05ea777d-e6c2-4071-a1c4-728832e3cfae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44035315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gp
io_stress_all.44035315
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.1124473841
Short name T47
Test name
Test status
Simulation time 63923169 ps
CPU time 0.58 seconds
Started May 30 02:31:52 PM PDT 24
Finished May 30 02:31:54 PM PDT 24
Peak memory 194092 kb
Host smart-950241fa-adb6-4241-963c-53eb3ad4706c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124473841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.1124473841
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.1488740554
Short name T344
Test name
Test status
Simulation time 46650155 ps
CPU time 0.67 seconds
Started May 30 02:31:53 PM PDT 24
Finished May 30 02:31:56 PM PDT 24
Peak memory 194164 kb
Host smart-4574a61b-5c6a-49b4-a045-8d05867b6f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488740554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.1488740554
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.2265971483
Short name T33
Test name
Test status
Simulation time 1205741649 ps
CPU time 18.91 seconds
Started May 30 02:31:54 PM PDT 24
Finished May 30 02:32:14 PM PDT 24
Peak memory 197992 kb
Host smart-852df129-dd9c-4407-9d51-47b827c1ea7c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265971483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.2265971483
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.3907141831
Short name T231
Test name
Test status
Simulation time 44473309 ps
CPU time 0.61 seconds
Started May 30 02:31:53 PM PDT 24
Finished May 30 02:31:55 PM PDT 24
Peak memory 194520 kb
Host smart-0697d356-02d2-4e67-8623-66e5fa742c35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907141831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.3907141831
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.2400850681
Short name T336
Test name
Test status
Simulation time 62006395 ps
CPU time 0.86 seconds
Started May 30 02:31:47 PM PDT 24
Finished May 30 02:31:51 PM PDT 24
Peak memory 196396 kb
Host smart-3d1fac0c-3b02-47b5-b171-855f8513821a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400850681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.2400850681
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.1289574146
Short name T319
Test name
Test status
Simulation time 394933815 ps
CPU time 1.37 seconds
Started May 30 02:31:55 PM PDT 24
Finished May 30 02:31:58 PM PDT 24
Peak memory 196476 kb
Host smart-55bb83c6-9101-4307-a8b4-c638404fd545
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289574146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.1289574146
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.3937006846
Short name T154
Test name
Test status
Simulation time 232665556 ps
CPU time 2.31 seconds
Started May 30 02:31:58 PM PDT 24
Finished May 30 02:32:02 PM PDT 24
Peak memory 196760 kb
Host smart-af069733-b2f0-4b26-b54e-f214a29e47c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937006846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.3937006846
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.2295691704
Short name T62
Test name
Test status
Simulation time 51699780 ps
CPU time 0.98 seconds
Started May 30 02:31:56 PM PDT 24
Finished May 30 02:31:59 PM PDT 24
Peak memory 195996 kb
Host smart-caf02c3e-4686-4444-9e2c-ec4cd2bf40fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295691704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.2295691704
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.3525005758
Short name T615
Test name
Test status
Simulation time 21693392 ps
CPU time 0.67 seconds
Started May 30 02:31:53 PM PDT 24
Finished May 30 02:31:56 PM PDT 24
Peak memory 194296 kb
Host smart-c4aea2cf-1265-47bc-a7d8-b5d9d49f3f3f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525005758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.3525005758
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.3254033630
Short name T293
Test name
Test status
Simulation time 143102419 ps
CPU time 5.57 seconds
Started May 30 02:31:48 PM PDT 24
Finished May 30 02:31:56 PM PDT 24
Peak memory 198076 kb
Host smart-3f9a306d-10e3-4939-9f04-da2be7c6c401
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254033630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.3254033630
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.860145892
Short name T457
Test name
Test status
Simulation time 377665023 ps
CPU time 1.07 seconds
Started May 30 02:31:57 PM PDT 24
Finished May 30 02:32:00 PM PDT 24
Peak memory 195884 kb
Host smart-532cf064-7165-405c-9332-7ca97502cf84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860145892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.860145892
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.253900184
Short name T646
Test name
Test status
Simulation time 331298381 ps
CPU time 1.66 seconds
Started May 30 02:31:58 PM PDT 24
Finished May 30 02:32:02 PM PDT 24
Peak memory 198008 kb
Host smart-146087c7-75d9-40dd-a5ef-5cb7baf63fda
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253900184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.253900184
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.1841249893
Short name T432
Test name
Test status
Simulation time 16845510861 ps
CPU time 119.83 seconds
Started May 30 02:31:52 PM PDT 24
Finished May 30 02:33:53 PM PDT 24
Peak memory 198196 kb
Host smart-63640243-f8c7-4b04-92ce-0c9065bb7e4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841249893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.1841249893
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.2882991308
Short name T590
Test name
Test status
Simulation time 752376224560 ps
CPU time 810.07 seconds
Started May 30 02:31:57 PM PDT 24
Finished May 30 02:45:29 PM PDT 24
Peak memory 198260 kb
Host smart-276698aa-fc97-4bcb-99f5-b3934c279236
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2882991308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.2882991308
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.286349504
Short name T308
Test name
Test status
Simulation time 12237437 ps
CPU time 0.61 seconds
Started May 30 02:31:52 PM PDT 24
Finished May 30 02:31:54 PM PDT 24
Peak memory 193936 kb
Host smart-a2ef7d4a-7afc-4846-b523-8cd506d8dea4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286349504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.286349504
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.2719894975
Short name T402
Test name
Test status
Simulation time 28388023 ps
CPU time 0.96 seconds
Started May 30 02:31:58 PM PDT 24
Finished May 30 02:32:01 PM PDT 24
Peak memory 195980 kb
Host smart-ba906453-31c2-40c5-8ddb-ff043e8c399f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719894975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.2719894975
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.2151966504
Short name T411
Test name
Test status
Simulation time 3051264023 ps
CPU time 25.3 seconds
Started May 30 02:31:57 PM PDT 24
Finished May 30 02:32:24 PM PDT 24
Peak memory 196928 kb
Host smart-12a12f5d-408a-41c9-805c-f096c8dff454
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151966504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.2151966504
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.2111901064
Short name T439
Test name
Test status
Simulation time 140726644 ps
CPU time 0.82 seconds
Started May 30 02:31:58 PM PDT 24
Finished May 30 02:32:01 PM PDT 24
Peak memory 196668 kb
Host smart-f41e8e73-ef3d-4a59-b732-65b580f43e95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111901064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.2111901064
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.2657978286
Short name T240
Test name
Test status
Simulation time 95177334 ps
CPU time 0.94 seconds
Started May 30 02:31:55 PM PDT 24
Finished May 30 02:31:58 PM PDT 24
Peak memory 196720 kb
Host smart-ff882e3a-d389-4395-bb4d-c9154a863eed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657978286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.2657978286
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.2880629119
Short name T491
Test name
Test status
Simulation time 87001377 ps
CPU time 3.41 seconds
Started May 30 02:31:53 PM PDT 24
Finished May 30 02:31:58 PM PDT 24
Peak memory 198008 kb
Host smart-bdedc69e-b2b9-4ec4-a67d-06daf3c342cd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880629119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.2880629119
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.3396063289
Short name T245
Test name
Test status
Simulation time 185459430 ps
CPU time 1.33 seconds
Started May 30 02:31:55 PM PDT 24
Finished May 30 02:31:58 PM PDT 24
Peak memory 197292 kb
Host smart-753a1179-00df-4e83-ab3d-f766886201dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396063289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.3396063289
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.4071447484
Short name T710
Test name
Test status
Simulation time 34071110 ps
CPU time 1.1 seconds
Started May 30 02:31:56 PM PDT 24
Finished May 30 02:31:59 PM PDT 24
Peak memory 196620 kb
Host smart-512524db-e164-403d-b04d-083bc424a8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071447484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.4071447484
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.4079723652
Short name T522
Test name
Test status
Simulation time 81312785 ps
CPU time 1.41 seconds
Started May 30 02:31:57 PM PDT 24
Finished May 30 02:32:00 PM PDT 24
Peak memory 197144 kb
Host smart-6ed1e360-6087-410f-a994-8747cc791268
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079723652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.4079723652
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.4245942614
Short name T20
Test name
Test status
Simulation time 312041074 ps
CPU time 4.13 seconds
Started May 30 02:31:56 PM PDT 24
Finished May 30 02:32:02 PM PDT 24
Peak memory 198000 kb
Host smart-c5349ed8-5471-44f5-8fb9-1ce813496a73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245942614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.4245942614
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.2510857082
Short name T592
Test name
Test status
Simulation time 123370962 ps
CPU time 0.93 seconds
Started May 30 02:31:57 PM PDT 24
Finished May 30 02:31:59 PM PDT 24
Peak memory 196356 kb
Host smart-2c5e4d63-e9d7-4b1d-adf2-8ec750772f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510857082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.2510857082
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.2222739811
Short name T394
Test name
Test status
Simulation time 162185040 ps
CPU time 1.28 seconds
Started May 30 02:31:47 PM PDT 24
Finished May 30 02:31:51 PM PDT 24
Peak memory 198056 kb
Host smart-72bd9f7e-7eca-4f8b-9907-85c11d89a984
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222739811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.2222739811
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.913299471
Short name T357
Test name
Test status
Simulation time 12144642658 ps
CPU time 64.76 seconds
Started May 30 02:31:58 PM PDT 24
Finished May 30 02:33:05 PM PDT 24
Peak memory 198164 kb
Host smart-d8af5b49-f2cd-4903-9b20-0b711f2a53a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913299471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.g
pio_stress_all.913299471
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.3799308103
Short name T596
Test name
Test status
Simulation time 13216603 ps
CPU time 0.58 seconds
Started May 30 02:30:55 PM PDT 24
Finished May 30 02:30:57 PM PDT 24
Peak memory 193904 kb
Host smart-44dc68e0-c33a-4ab7-a790-48b300040cfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799308103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.3799308103
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.1439866320
Short name T470
Test name
Test status
Simulation time 44211993 ps
CPU time 0.87 seconds
Started May 30 02:30:56 PM PDT 24
Finished May 30 02:30:58 PM PDT 24
Peak memory 196028 kb
Host smart-41c602c4-b9a6-4e20-925c-9b267caac93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439866320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.1439866320
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.1336852758
Short name T234
Test name
Test status
Simulation time 854355433 ps
CPU time 9.31 seconds
Started May 30 02:30:57 PM PDT 24
Finished May 30 02:31:07 PM PDT 24
Peak memory 196704 kb
Host smart-8c3d545c-2719-47a2-afbb-71babe39ef35
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336852758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.1336852758
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.3848594971
Short name T15
Test name
Test status
Simulation time 27452144 ps
CPU time 0.7 seconds
Started May 30 02:30:55 PM PDT 24
Finished May 30 02:30:57 PM PDT 24
Peak memory 194448 kb
Host smart-6b2e6228-6bc0-486b-9ebf-bd757efdb951
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848594971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.3848594971
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.446206953
Short name T385
Test name
Test status
Simulation time 31338139 ps
CPU time 0.86 seconds
Started May 30 02:30:59 PM PDT 24
Finished May 30 02:31:00 PM PDT 24
Peak memory 195512 kb
Host smart-c6045302-a8f5-4a17-bd7c-ba9e228c62dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446206953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.446206953
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.3510890757
Short name T117
Test name
Test status
Simulation time 168248988 ps
CPU time 3.78 seconds
Started May 30 02:31:02 PM PDT 24
Finished May 30 02:31:06 PM PDT 24
Peak memory 196376 kb
Host smart-0ff23e04-66c3-4b3c-a4c7-6d1eedbad94b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510890757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.3510890757
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.685601608
Short name T466
Test name
Test status
Simulation time 385438631 ps
CPU time 2.3 seconds
Started May 30 02:30:55 PM PDT 24
Finished May 30 02:30:59 PM PDT 24
Peak memory 195832 kb
Host smart-2e8e5c8c-597c-401f-8482-5f5d63d4d311
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685601608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.685601608
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.2325602896
Short name T211
Test name
Test status
Simulation time 115918430 ps
CPU time 1.21 seconds
Started May 30 02:30:41 PM PDT 24
Finished May 30 02:30:44 PM PDT 24
Peak memory 198064 kb
Host smart-fdd7109c-498b-4a24-bd9c-051e54af6c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325602896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.2325602896
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.2369583285
Short name T451
Test name
Test status
Simulation time 18612956 ps
CPU time 0.73 seconds
Started May 30 02:30:52 PM PDT 24
Finished May 30 02:30:55 PM PDT 24
Peak memory 195492 kb
Host smart-b047a8f1-ed46-4f97-b8bf-5e429dbeb62a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369583285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.2369583285
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.1526031788
Short name T327
Test name
Test status
Simulation time 462781316 ps
CPU time 2.18 seconds
Started May 30 02:30:53 PM PDT 24
Finished May 30 02:30:57 PM PDT 24
Peak memory 197956 kb
Host smart-7d54964d-2193-4100-a509-638aa96ddd2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526031788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.1526031788
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_smoke.1141656282
Short name T161
Test name
Test status
Simulation time 49184104 ps
CPU time 1.27 seconds
Started May 30 02:30:38 PM PDT 24
Finished May 30 02:30:41 PM PDT 24
Peak memory 195672 kb
Host smart-7c6b6d94-d444-4eea-a6c0-aef6a30b2710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141656282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.1141656282
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.3617756104
Short name T283
Test name
Test status
Simulation time 413077737 ps
CPU time 1.06 seconds
Started May 30 02:30:42 PM PDT 24
Finished May 30 02:30:44 PM PDT 24
Peak memory 195780 kb
Host smart-de2bfe65-f5cc-492e-ba9c-18c1b025258d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617756104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.3617756104
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.4053373167
Short name T426
Test name
Test status
Simulation time 21557310692 ps
CPU time 159.58 seconds
Started May 30 02:30:55 PM PDT 24
Finished May 30 02:33:35 PM PDT 24
Peak memory 198220 kb
Host smart-45973a83-596a-4438-8ebc-7213bc7b1b33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053373167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.4053373167
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.4126131739
Short name T499
Test name
Test status
Simulation time 84043196464 ps
CPU time 2081.08 seconds
Started May 30 02:30:53 PM PDT 24
Finished May 30 03:05:36 PM PDT 24
Peak memory 198272 kb
Host smart-f466bd7f-a19b-46c8-8b97-4e34b2038622
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4126131739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.4126131739
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.2828293150
Short name T61
Test name
Test status
Simulation time 42945513 ps
CPU time 0.57 seconds
Started May 30 02:31:57 PM PDT 24
Finished May 30 02:32:00 PM PDT 24
Peak memory 194616 kb
Host smart-44839290-8607-4a07-a25a-333f32e48819
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828293150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.2828293150
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.156679461
Short name T217
Test name
Test status
Simulation time 30560249 ps
CPU time 0.74 seconds
Started May 30 02:31:57 PM PDT 24
Finished May 30 02:32:00 PM PDT 24
Peak memory 196168 kb
Host smart-4889dc63-3fe6-4bbc-93ce-b10161ecb1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156679461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.156679461
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.604010948
Short name T364
Test name
Test status
Simulation time 625807762 ps
CPU time 16.58 seconds
Started May 30 02:31:57 PM PDT 24
Finished May 30 02:32:15 PM PDT 24
Peak memory 197160 kb
Host smart-199ad640-6676-4ea0-a71f-6d0b5e2fd058
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604010948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stres
s.604010948
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.3504736243
Short name T9
Test name
Test status
Simulation time 56707934 ps
CPU time 0.91 seconds
Started May 30 02:31:48 PM PDT 24
Finished May 30 02:31:51 PM PDT 24
Peak memory 196896 kb
Host smart-c762957b-7b45-4cf9-a417-9e48abbeddc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504736243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.3504736243
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.2978215708
Short name T378
Test name
Test status
Simulation time 163315895 ps
CPU time 1.13 seconds
Started May 30 02:31:55 PM PDT 24
Finished May 30 02:31:58 PM PDT 24
Peak memory 196084 kb
Host smart-3d8a785b-840e-482d-a783-7abd1f1e9d0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978215708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.2978215708
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.3577848884
Short name T443
Test name
Test status
Simulation time 48359808 ps
CPU time 2.23 seconds
Started May 30 02:31:56 PM PDT 24
Finished May 30 02:31:59 PM PDT 24
Peak memory 198052 kb
Host smart-ce7434c5-b3d0-44f5-b81e-83a5e90e648c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577848884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.3577848884
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.154150282
Short name T462
Test name
Test status
Simulation time 93496439 ps
CPU time 2.24 seconds
Started May 30 02:31:56 PM PDT 24
Finished May 30 02:32:00 PM PDT 24
Peak memory 197364 kb
Host smart-28fa58dc-590f-4454-b003-482660595475
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154150282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger.
154150282
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.1756516231
Short name T709
Test name
Test status
Simulation time 75234188 ps
CPU time 1.35 seconds
Started May 30 02:31:57 PM PDT 24
Finished May 30 02:32:00 PM PDT 24
Peak memory 197124 kb
Host smart-e83214a6-6df3-4247-b0ad-0f278d96b9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756516231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.1756516231
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.1529695330
Short name T131
Test name
Test status
Simulation time 85381722 ps
CPU time 0.78 seconds
Started May 30 02:31:57 PM PDT 24
Finished May 30 02:32:00 PM PDT 24
Peak memory 195472 kb
Host smart-c733d362-fbe3-4a27-86be-73f9bb31c3f4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529695330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.1529695330
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.3725771308
Short name T413
Test name
Test status
Simulation time 106683139 ps
CPU time 5.27 seconds
Started May 30 02:31:57 PM PDT 24
Finished May 30 02:32:04 PM PDT 24
Peak memory 198008 kb
Host smart-a78d2fdb-4dce-4d3a-919b-dac3b3b3a603
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725771308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.3725771308
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.3798857330
Short name T580
Test name
Test status
Simulation time 23682575 ps
CPU time 0.75 seconds
Started May 30 02:31:47 PM PDT 24
Finished May 30 02:31:50 PM PDT 24
Peak memory 194216 kb
Host smart-db639756-3487-4366-997d-1e1ed00c54ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798857330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.3798857330
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.891283461
Short name T424
Test name
Test status
Simulation time 573967774 ps
CPU time 1.24 seconds
Started May 30 02:31:57 PM PDT 24
Finished May 30 02:32:01 PM PDT 24
Peak memory 196644 kb
Host smart-a83f1712-7451-4d5d-beab-fb2e025ae5ed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891283461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.891283461
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.2870597735
Short name T584
Test name
Test status
Simulation time 12203664365 ps
CPU time 159.26 seconds
Started May 30 02:31:56 PM PDT 24
Finished May 30 02:34:37 PM PDT 24
Peak memory 198188 kb
Host smart-f6c178be-ebe0-4955-8844-fb59dfb3e285
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870597735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.2870597735
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.3306031812
Short name T632
Test name
Test status
Simulation time 36341026 ps
CPU time 0.57 seconds
Started May 30 02:31:57 PM PDT 24
Finished May 30 02:32:00 PM PDT 24
Peak memory 193948 kb
Host smart-73add4f8-c7ad-4696-9ab1-32e013cce3d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306031812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.3306031812
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.2631133593
Short name T199
Test name
Test status
Simulation time 66908505 ps
CPU time 0.81 seconds
Started May 30 02:31:55 PM PDT 24
Finished May 30 02:31:57 PM PDT 24
Peak memory 196588 kb
Host smart-99199897-2d0a-4b3f-a7e2-6ed528a5c10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631133593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.2631133593
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.3599485730
Short name T513
Test name
Test status
Simulation time 134426017 ps
CPU time 4.39 seconds
Started May 30 02:31:58 PM PDT 24
Finished May 30 02:32:05 PM PDT 24
Peak memory 196780 kb
Host smart-eadfdd00-9a85-4d3a-8c95-40f0ff109ece
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599485730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.3599485730
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.1428822584
Short name T301
Test name
Test status
Simulation time 29273939 ps
CPU time 0.77 seconds
Started May 30 02:31:58 PM PDT 24
Finished May 30 02:32:01 PM PDT 24
Peak memory 194804 kb
Host smart-1f537d03-c088-48d5-975c-ab56ea49e0c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428822584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.1428822584
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.3293937276
Short name T166
Test name
Test status
Simulation time 163213188 ps
CPU time 0.97 seconds
Started May 30 02:31:58 PM PDT 24
Finished May 30 02:32:01 PM PDT 24
Peak memory 196932 kb
Host smart-368a66d1-a8f8-44cf-8a59-0549eca3814c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293937276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.3293937276
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.3131809827
Short name T59
Test name
Test status
Simulation time 82719193 ps
CPU time 3.49 seconds
Started May 30 02:32:00 PM PDT 24
Finished May 30 02:32:06 PM PDT 24
Peak memory 196468 kb
Host smart-18ab98cf-d192-45b6-ab2e-c4370218f754
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131809827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.3131809827
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.3720013776
Short name T26
Test name
Test status
Simulation time 42111083 ps
CPU time 1.27 seconds
Started May 30 02:32:00 PM PDT 24
Finished May 30 02:32:04 PM PDT 24
Peak memory 196572 kb
Host smart-19fd0ee2-eded-48e7-b118-63fcc8249a98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720013776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.3720013776
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.2925844425
Short name T222
Test name
Test status
Simulation time 182649255 ps
CPU time 1.34 seconds
Started May 30 02:31:56 PM PDT 24
Finished May 30 02:31:59 PM PDT 24
Peak memory 195808 kb
Host smart-c1b07ba1-9ba3-4e45-a995-74f748ca3af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925844425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.2925844425
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.1192917590
Short name T711
Test name
Test status
Simulation time 64897766 ps
CPU time 0.74 seconds
Started May 30 02:31:55 PM PDT 24
Finished May 30 02:31:57 PM PDT 24
Peak memory 196228 kb
Host smart-edad79cc-cd99-47b3-a3ad-a180580bdf91
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192917590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.1192917590
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.768591831
Short name T354
Test name
Test status
Simulation time 1043549198 ps
CPU time 3.23 seconds
Started May 30 02:31:59 PM PDT 24
Finished May 30 02:32:05 PM PDT 24
Peak memory 198024 kb
Host smart-3a721d54-cdc3-4c5d-9be2-5396ff5dc8db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768591831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ran
dom_long_reg_writes_reg_reads.768591831
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.3215967650
Short name T518
Test name
Test status
Simulation time 328889798 ps
CPU time 1.59 seconds
Started May 30 02:31:57 PM PDT 24
Finished May 30 02:32:01 PM PDT 24
Peak memory 196704 kb
Host smart-3d36b65a-bfd1-4077-9129-5a3ba9cd3a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215967650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.3215967650
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.3854941947
Short name T534
Test name
Test status
Simulation time 133851538 ps
CPU time 0.77 seconds
Started May 30 02:31:57 PM PDT 24
Finished May 30 02:32:00 PM PDT 24
Peak memory 195316 kb
Host smart-a5ea5eb8-6019-4945-b432-84f78a84854c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854941947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.3854941947
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.3282569226
Short name T401
Test name
Test status
Simulation time 2359961740 ps
CPU time 32.28 seconds
Started May 30 02:31:57 PM PDT 24
Finished May 30 02:32:32 PM PDT 24
Peak memory 198212 kb
Host smart-4aafa449-e255-426a-ab28-7f28eb8519fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282569226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.3282569226
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.971706235
Short name T611
Test name
Test status
Simulation time 13474233 ps
CPU time 0.61 seconds
Started May 30 02:32:01 PM PDT 24
Finished May 30 02:32:03 PM PDT 24
Peak memory 193884 kb
Host smart-60825f55-2638-4822-92c2-18ea7d99b212
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971706235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.971706235
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.2027154451
Short name T694
Test name
Test status
Simulation time 22853848 ps
CPU time 0.72 seconds
Started May 30 02:31:57 PM PDT 24
Finished May 30 02:31:59 PM PDT 24
Peak memory 194268 kb
Host smart-56a94e55-bf31-4031-836e-49cc62413624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027154451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.2027154451
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.865495622
Short name T687
Test name
Test status
Simulation time 570981805 ps
CPU time 20.09 seconds
Started May 30 02:32:00 PM PDT 24
Finished May 30 02:32:23 PM PDT 24
Peak memory 197180 kb
Host smart-8f41118f-8f43-4a98-bc71-915787621825
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865495622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stres
s.865495622
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.1056581719
Short name T160
Test name
Test status
Simulation time 53180083 ps
CPU time 0.93 seconds
Started May 30 02:32:00 PM PDT 24
Finished May 30 02:32:03 PM PDT 24
Peak memory 196720 kb
Host smart-00194d90-3dd7-464f-9df8-5f3503acd2a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056581719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.1056581719
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.1048602409
Short name T24
Test name
Test status
Simulation time 73162089 ps
CPU time 1.29 seconds
Started May 30 02:32:00 PM PDT 24
Finished May 30 02:32:04 PM PDT 24
Peak memory 196668 kb
Host smart-3f9203a0-00e5-43b3-8b09-28c8b854960f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048602409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.1048602409
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.4093204187
Short name T113
Test name
Test status
Simulation time 28280666 ps
CPU time 1.29 seconds
Started May 30 02:32:00 PM PDT 24
Finished May 30 02:32:04 PM PDT 24
Peak memory 198140 kb
Host smart-0df55c4e-02e8-4dfb-9a82-756ec2652c0b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093204187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.4093204187
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.3863767301
Short name T464
Test name
Test status
Simulation time 114723832 ps
CPU time 1.55 seconds
Started May 30 02:31:59 PM PDT 24
Finished May 30 02:32:03 PM PDT 24
Peak memory 196156 kb
Host smart-2893ec3b-e936-4bd4-9e5a-19edb9aeba9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863767301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.3863767301
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.1620105962
Short name T122
Test name
Test status
Simulation time 88583523 ps
CPU time 0.85 seconds
Started May 30 02:31:57 PM PDT 24
Finished May 30 02:32:00 PM PDT 24
Peak memory 196824 kb
Host smart-d9fb98f3-da3c-4969-b019-5689af649357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620105962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.1620105962
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.2895350050
Short name T285
Test name
Test status
Simulation time 72055186 ps
CPU time 1.26 seconds
Started May 30 02:32:02 PM PDT 24
Finished May 30 02:32:05 PM PDT 24
Peak memory 196968 kb
Host smart-f4833138-4aea-4521-9c9d-c885e78252d4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895350050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.2895350050
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.3489678755
Short name T612
Test name
Test status
Simulation time 1005735058 ps
CPU time 2.99 seconds
Started May 30 02:31:59 PM PDT 24
Finished May 30 02:32:05 PM PDT 24
Peak memory 197200 kb
Host smart-594f8c22-0d45-48db-a882-30bf21e85a03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489678755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.3489678755
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.2032067772
Short name T539
Test name
Test status
Simulation time 239766742 ps
CPU time 1.22 seconds
Started May 30 02:31:59 PM PDT 24
Finished May 30 02:32:03 PM PDT 24
Peak memory 196636 kb
Host smart-979f9046-273d-4c43-b053-5569fe5deea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032067772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.2032067772
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.4262256855
Short name T17
Test name
Test status
Simulation time 79785580 ps
CPU time 1.29 seconds
Started May 30 02:31:57 PM PDT 24
Finished May 30 02:32:01 PM PDT 24
Peak memory 195884 kb
Host smart-9034f300-ed59-4ca2-a550-4f4bf2048f81
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262256855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.4262256855
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.647337699
Short name T610
Test name
Test status
Simulation time 9356544319 ps
CPU time 82.69 seconds
Started May 30 02:32:02 PM PDT 24
Finished May 30 02:33:26 PM PDT 24
Peak memory 198148 kb
Host smart-ea6a548f-8e3f-4e74-8e02-13a28a4d5eb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647337699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.g
pio_stress_all.647337699
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.1657859505
Short name T558
Test name
Test status
Simulation time 15310693 ps
CPU time 0.6 seconds
Started May 30 02:31:59 PM PDT 24
Finished May 30 02:32:03 PM PDT 24
Peak memory 194156 kb
Host smart-d975a29d-b560-4655-b79c-11077ef7c34f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657859505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.1657859505
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.2030682917
Short name T560
Test name
Test status
Simulation time 22822485 ps
CPU time 0.77 seconds
Started May 30 02:31:58 PM PDT 24
Finished May 30 02:32:01 PM PDT 24
Peak memory 195484 kb
Host smart-e381564f-9474-4f3c-92f2-2d130a368320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030682917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.2030682917
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.2269891467
Short name T264
Test name
Test status
Simulation time 786514694 ps
CPU time 10.49 seconds
Started May 30 02:31:59 PM PDT 24
Finished May 30 02:32:12 PM PDT 24
Peak memory 195540 kb
Host smart-18c019a7-a9d3-4606-879a-08a97a0b27b9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269891467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.2269891467
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.2833792845
Short name T696
Test name
Test status
Simulation time 140242407 ps
CPU time 0.95 seconds
Started May 30 02:32:01 PM PDT 24
Finished May 30 02:32:04 PM PDT 24
Peak memory 196652 kb
Host smart-034abf24-e897-4073-bca7-092596e28679
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833792845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.2833792845
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.2193388637
Short name T545
Test name
Test status
Simulation time 587175765 ps
CPU time 1.17 seconds
Started May 30 02:32:04 PM PDT 24
Finished May 30 02:32:06 PM PDT 24
Peak memory 196696 kb
Host smart-c72af406-da0d-4316-8c92-efd4e05350c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193388637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.2193388637
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.2060906225
Short name T643
Test name
Test status
Simulation time 28850938 ps
CPU time 1.34 seconds
Started May 30 02:31:59 PM PDT 24
Finished May 30 02:32:02 PM PDT 24
Peak memory 196972 kb
Host smart-c8a1d63b-e64e-4bc1-a456-df5766b819a0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060906225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.2060906225
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.1918853510
Short name T136
Test name
Test status
Simulation time 60097546 ps
CPU time 1.22 seconds
Started May 30 02:31:59 PM PDT 24
Finished May 30 02:32:03 PM PDT 24
Peak memory 195788 kb
Host smart-22e267dd-28b8-405b-bcbb-7310c56ce680
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918853510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.1918853510
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.3714026518
Short name T250
Test name
Test status
Simulation time 25450748 ps
CPU time 0.75 seconds
Started May 30 02:32:01 PM PDT 24
Finished May 30 02:32:04 PM PDT 24
Peak memory 195380 kb
Host smart-8a8299d0-278b-4ea9-aa2d-b6e8b773c180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714026518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.3714026518
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.1602449639
Short name T343
Test name
Test status
Simulation time 114705420 ps
CPU time 1.31 seconds
Started May 30 02:31:58 PM PDT 24
Finished May 30 02:32:02 PM PDT 24
Peak memory 196104 kb
Host smart-e9768c99-5c88-4bfe-81ee-63f7a3608307
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602449639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.1602449639
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.2995306611
Short name T678
Test name
Test status
Simulation time 229971653 ps
CPU time 3.01 seconds
Started May 30 02:31:58 PM PDT 24
Finished May 30 02:32:04 PM PDT 24
Peak memory 198024 kb
Host smart-da1120ee-2795-43cc-802c-1c1de750c77e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995306611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.2995306611
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.802601133
Short name T635
Test name
Test status
Simulation time 112608616 ps
CPU time 1.51 seconds
Started May 30 02:31:59 PM PDT 24
Finished May 30 02:32:04 PM PDT 24
Peak memory 197204 kb
Host smart-6be9d592-a8ff-42be-82d5-f44446cafa2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802601133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.802601133
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.3817162332
Short name T305
Test name
Test status
Simulation time 168595764 ps
CPU time 1.13 seconds
Started May 30 02:31:58 PM PDT 24
Finished May 30 02:32:02 PM PDT 24
Peak memory 196596 kb
Host smart-0df880fb-d509-48ea-8675-495b0eca8dd9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817162332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.3817162332
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.167800621
Short name T175
Test name
Test status
Simulation time 8030430104 ps
CPU time 208.53 seconds
Started May 30 02:32:02 PM PDT 24
Finished May 30 02:35:32 PM PDT 24
Peak memory 198072 kb
Host smart-56da0b4e-9db5-4adf-a311-ba56cb06bb63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167800621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.g
pio_stress_all.167800621
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.988068893
Short name T437
Test name
Test status
Simulation time 196094897252 ps
CPU time 1240.93 seconds
Started May 30 02:31:57 PM PDT 24
Finished May 30 02:52:40 PM PDT 24
Peak memory 198332 kb
Host smart-3c86188b-f517-4201-900f-ad9f12dc4c1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=988068893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.988068893
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.640508854
Short name T314
Test name
Test status
Simulation time 12365103 ps
CPU time 0.58 seconds
Started May 30 02:32:02 PM PDT 24
Finished May 30 02:32:04 PM PDT 24
Peak memory 194592 kb
Host smart-21bf0773-46ab-4fe7-b426-7204a8449260
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640508854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.640508854
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.3865033920
Short name T468
Test name
Test status
Simulation time 42162478 ps
CPU time 0.97 seconds
Started May 30 02:31:59 PM PDT 24
Finished May 30 02:32:03 PM PDT 24
Peak memory 197400 kb
Host smart-5d582050-3728-47f8-8ce6-89f2fd3cfae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865033920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.3865033920
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.351239319
Short name T614
Test name
Test status
Simulation time 882488372 ps
CPU time 14.16 seconds
Started May 30 02:32:00 PM PDT 24
Finished May 30 02:32:16 PM PDT 24
Peak memory 196876 kb
Host smart-be7ff287-a561-4ef3-b7b7-acbd8b7782c8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351239319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stres
s.351239319
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.1268203050
Short name T701
Test name
Test status
Simulation time 193346482 ps
CPU time 0.86 seconds
Started May 30 02:32:02 PM PDT 24
Finished May 30 02:32:05 PM PDT 24
Peak memory 195968 kb
Host smart-48fe7d1f-6739-49c8-93bc-f93a78bd14a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268203050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.1268203050
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.3258635994
Short name T173
Test name
Test status
Simulation time 168580372 ps
CPU time 0.99 seconds
Started May 30 02:32:01 PM PDT 24
Finished May 30 02:32:04 PM PDT 24
Peak memory 195836 kb
Host smart-5ccfcef5-fd41-45c8-8b4b-092549644ba0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258635994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.3258635994
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.3070886710
Short name T414
Test name
Test status
Simulation time 182654876 ps
CPU time 2.01 seconds
Started May 30 02:31:59 PM PDT 24
Finished May 30 02:32:04 PM PDT 24
Peak memory 198152 kb
Host smart-b960d062-cb0d-45d6-9378-613673aa4e13
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070886710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.3070886710
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.269045613
Short name T137
Test name
Test status
Simulation time 220199436 ps
CPU time 1.92 seconds
Started May 30 02:31:58 PM PDT 24
Finished May 30 02:32:03 PM PDT 24
Peak memory 196580 kb
Host smart-2eaff47f-c17f-4367-ad3e-3a045dda9e06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269045613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger.
269045613
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.31667028
Short name T63
Test name
Test status
Simulation time 30966465 ps
CPU time 0.86 seconds
Started May 30 02:32:00 PM PDT 24
Finished May 30 02:32:04 PM PDT 24
Peak memory 195588 kb
Host smart-214952cb-f648-4051-883b-2b3028fdbe42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31667028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.31667028
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.771875767
Short name T204
Test name
Test status
Simulation time 481978964 ps
CPU time 1.31 seconds
Started May 30 02:32:00 PM PDT 24
Finished May 30 02:32:04 PM PDT 24
Peak memory 198008 kb
Host smart-785d1d51-f54a-40dc-aae7-923e328ec4f6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771875767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullup
_pulldown.771875767
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.3363936011
Short name T110
Test name
Test status
Simulation time 1088075064 ps
CPU time 4.84 seconds
Started May 30 02:31:59 PM PDT 24
Finished May 30 02:32:07 PM PDT 24
Peak memory 197852 kb
Host smart-03261ba7-544a-466d-92f1-ddeff600172b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363936011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.3363936011
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.1813601231
Short name T690
Test name
Test status
Simulation time 130176429 ps
CPU time 0.93 seconds
Started May 30 02:31:58 PM PDT 24
Finished May 30 02:32:02 PM PDT 24
Peak memory 196400 kb
Host smart-50e6b8e8-1677-45c5-87aa-8e3c26b372b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813601231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.1813601231
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2526997235
Short name T220
Test name
Test status
Simulation time 64586002 ps
CPU time 0.85 seconds
Started May 30 02:32:04 PM PDT 24
Finished May 30 02:32:06 PM PDT 24
Peak memory 196124 kb
Host smart-a08d0464-de04-42f3-8f6d-5208b27badb5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526997235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2526997235
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.848605179
Short name T282
Test name
Test status
Simulation time 22648377604 ps
CPU time 52.65 seconds
Started May 30 02:31:59 PM PDT 24
Finished May 30 02:32:54 PM PDT 24
Peak memory 198164 kb
Host smart-07cf1230-f1fe-442a-be3a-3b6195ee5866
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848605179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.g
pio_stress_all.848605179
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.1012859056
Short name T666
Test name
Test status
Simulation time 80489936860 ps
CPU time 569.02 seconds
Started May 30 02:31:57 PM PDT 24
Finished May 30 02:41:29 PM PDT 24
Peak memory 198316 kb
Host smart-45476540-9521-401c-9af8-3947a3879aab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1012859056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.1012859056
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.3588531382
Short name T269
Test name
Test status
Simulation time 13808207 ps
CPU time 0.61 seconds
Started May 30 02:32:08 PM PDT 24
Finished May 30 02:32:09 PM PDT 24
Peak memory 193948 kb
Host smart-484dba3d-730f-492c-ba10-b529981f4d21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588531382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.3588531382
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.1313749235
Short name T460
Test name
Test status
Simulation time 27417356 ps
CPU time 0.64 seconds
Started May 30 02:32:01 PM PDT 24
Finished May 30 02:32:04 PM PDT 24
Peak memory 193948 kb
Host smart-00bdd823-3f01-49f5-8244-65d276ae331e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313749235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.1313749235
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.3850446514
Short name T650
Test name
Test status
Simulation time 1541956044 ps
CPU time 22.93 seconds
Started May 30 02:32:11 PM PDT 24
Finished May 30 02:32:35 PM PDT 24
Peak memory 198056 kb
Host smart-20d81123-6c3a-47a5-aed2-119407a625d2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850446514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.3850446514
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2188857124
Short name T644
Test name
Test status
Simulation time 56039884 ps
CPU time 0.7 seconds
Started May 30 02:32:12 PM PDT 24
Finished May 30 02:32:15 PM PDT 24
Peak memory 194768 kb
Host smart-d1c6556d-ab22-4efc-b26f-e38d703b473e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188857124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2188857124
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.3948373947
Short name T241
Test name
Test status
Simulation time 309226443 ps
CPU time 0.99 seconds
Started May 30 02:32:00 PM PDT 24
Finished May 30 02:32:04 PM PDT 24
Peak memory 195860 kb
Host smart-9a4ca7ba-b170-4e22-9f5b-606f8be6a4e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948373947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.3948373947
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.4196487935
Short name T286
Test name
Test status
Simulation time 43709713 ps
CPU time 1.73 seconds
Started May 30 02:32:13 PM PDT 24
Finished May 30 02:32:17 PM PDT 24
Peak memory 196312 kb
Host smart-d1fc9675-62df-4b86-ab25-c4198f6a11ac
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196487935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.4196487935
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.3917130891
Short name T132
Test name
Test status
Simulation time 67997958 ps
CPU time 1.73 seconds
Started May 30 02:32:10 PM PDT 24
Finished May 30 02:32:13 PM PDT 24
Peak memory 196772 kb
Host smart-a74ef4f0-8432-46e4-af59-ff26d0116bd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917130891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.3917130891
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.339991411
Short name T571
Test name
Test status
Simulation time 23031877 ps
CPU time 0.88 seconds
Started May 30 02:32:02 PM PDT 24
Finished May 30 02:32:04 PM PDT 24
Peak memory 195980 kb
Host smart-927126ef-6df0-4127-9c0f-8096b3a07294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339991411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.339991411
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.2942868117
Short name T365
Test name
Test status
Simulation time 27557601 ps
CPU time 1.13 seconds
Started May 30 02:32:00 PM PDT 24
Finished May 30 02:32:04 PM PDT 24
Peak memory 196188 kb
Host smart-dfc10cbc-fbc3-4999-8c24-c812fe488542
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942868117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.2942868117
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.2831565645
Short name T445
Test name
Test status
Simulation time 2063285911 ps
CPU time 6.04 seconds
Started May 30 02:32:14 PM PDT 24
Finished May 30 02:32:22 PM PDT 24
Peak memory 198048 kb
Host smart-228625be-0ff6-4fa8-9ad9-170c32b5abe5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831565645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.2831565645
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.2496108816
Short name T533
Test name
Test status
Simulation time 175075894 ps
CPU time 1.32 seconds
Started May 30 02:32:01 PM PDT 24
Finished May 30 02:32:05 PM PDT 24
Peak memory 196888 kb
Host smart-14d795b7-643d-4704-9842-19e36b821976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496108816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.2496108816
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.2304329938
Short name T263
Test name
Test status
Simulation time 57035870 ps
CPU time 1.38 seconds
Started May 30 02:32:04 PM PDT 24
Finished May 30 02:32:07 PM PDT 24
Peak memory 195572 kb
Host smart-9cc227ca-c456-43bb-8603-ae57778833c7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304329938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.2304329938
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.2635733115
Short name T685
Test name
Test status
Simulation time 12204763523 ps
CPU time 92.32 seconds
Started May 30 02:32:12 PM PDT 24
Finished May 30 02:33:46 PM PDT 24
Peak memory 198236 kb
Host smart-596b1c6d-6c09-49e0-90b4-2977b56f91c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635733115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.2635733115
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.3191852285
Short name T559
Test name
Test status
Simulation time 35614360 ps
CPU time 0.59 seconds
Started May 30 02:32:12 PM PDT 24
Finished May 30 02:32:14 PM PDT 24
Peak memory 194696 kb
Host smart-24ce4c8e-0728-4831-a776-32e4749ba97a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191852285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.3191852285
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.1034103241
Short name T177
Test name
Test status
Simulation time 15403267 ps
CPU time 0.62 seconds
Started May 30 02:32:13 PM PDT 24
Finished May 30 02:32:15 PM PDT 24
Peak memory 194652 kb
Host smart-4dc88e2d-7462-47a1-8d70-9e4b67897ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034103241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.1034103241
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.236151479
Short name T200
Test name
Test status
Simulation time 216158548 ps
CPU time 8.07 seconds
Started May 30 02:32:15 PM PDT 24
Finished May 30 02:32:25 PM PDT 24
Peak memory 197152 kb
Host smart-336569aa-1dac-405d-b6c7-58f3f0e973fb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236151479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stres
s.236151479
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.3523704390
Short name T587
Test name
Test status
Simulation time 70927974 ps
CPU time 0.94 seconds
Started May 30 02:32:09 PM PDT 24
Finished May 30 02:32:11 PM PDT 24
Peak memory 197768 kb
Host smart-bb88c3ea-20fe-4137-bc4e-102161b4b099
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523704390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.3523704390
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.2611077107
Short name T138
Test name
Test status
Simulation time 360504088 ps
CPU time 1.12 seconds
Started May 30 02:32:12 PM PDT 24
Finished May 30 02:32:15 PM PDT 24
Peak memory 196060 kb
Host smart-6c551a2c-01bb-4397-ac3d-c3e7f2cb46f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611077107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.2611077107
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.3042114425
Short name T258
Test name
Test status
Simulation time 201503492 ps
CPU time 2.11 seconds
Started May 30 02:32:09 PM PDT 24
Finished May 30 02:32:12 PM PDT 24
Peak memory 197920 kb
Host smart-bc69e550-89b9-4cb3-8c02-9964d6e582eb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042114425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.3042114425
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.420753421
Short name T295
Test name
Test status
Simulation time 50355746 ps
CPU time 1.7 seconds
Started May 30 02:32:09 PM PDT 24
Finished May 30 02:32:11 PM PDT 24
Peak memory 195904 kb
Host smart-d0321fe3-a014-40ef-a3ee-acf6659e8ddc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420753421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger.
420753421
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.3080321067
Short name T304
Test name
Test status
Simulation time 109307063 ps
CPU time 0.74 seconds
Started May 30 02:32:10 PM PDT 24
Finished May 30 02:32:12 PM PDT 24
Peak memory 196224 kb
Host smart-647b92d9-b9b0-4259-9686-b3232bab1d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080321067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.3080321067
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.2933039613
Short name T664
Test name
Test status
Simulation time 52336967 ps
CPU time 0.68 seconds
Started May 30 02:32:09 PM PDT 24
Finished May 30 02:32:10 PM PDT 24
Peak memory 194456 kb
Host smart-1b9fde61-7088-473d-9739-cd008eb4079f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933039613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.2933039613
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.346641169
Short name T8
Test name
Test status
Simulation time 386483023 ps
CPU time 4.91 seconds
Started May 30 02:32:11 PM PDT 24
Finished May 30 02:32:18 PM PDT 24
Peak memory 198124 kb
Host smart-d044fe31-f1ab-4e93-b2f4-86cee84c1023
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346641169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ran
dom_long_reg_writes_reg_reads.346641169
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.3790284468
Short name T298
Test name
Test status
Simulation time 145345380 ps
CPU time 1.24 seconds
Started May 30 02:32:14 PM PDT 24
Finished May 30 02:32:17 PM PDT 24
Peak memory 196944 kb
Host smart-0a929a24-7c3d-4f46-a245-794598fa5510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790284468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.3790284468
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.246848665
Short name T352
Test name
Test status
Simulation time 187790971 ps
CPU time 1.54 seconds
Started May 30 02:32:11 PM PDT 24
Finished May 30 02:32:13 PM PDT 24
Peak memory 196708 kb
Host smart-80c8caa2-e8ff-4b3d-b9e8-6075f53526a3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246848665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.246848665
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.719988695
Short name T141
Test name
Test status
Simulation time 1320543111 ps
CPU time 32.13 seconds
Started May 30 02:32:14 PM PDT 24
Finished May 30 02:32:48 PM PDT 24
Peak memory 198060 kb
Host smart-39cf5a6f-cf80-4986-b13c-1c749a726cc2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719988695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.g
pio_stress_all.719988695
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.3133806018
Short name T276
Test name
Test status
Simulation time 79852411 ps
CPU time 0.6 seconds
Started May 30 02:32:12 PM PDT 24
Finished May 30 02:32:14 PM PDT 24
Peak memory 194060 kb
Host smart-aa88d205-6635-4e24-bbea-ed738cabc1bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133806018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.3133806018
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.247701729
Short name T496
Test name
Test status
Simulation time 86372080 ps
CPU time 0.85 seconds
Started May 30 02:32:09 PM PDT 24
Finished May 30 02:32:11 PM PDT 24
Peak memory 195380 kb
Host smart-142f5358-61a5-476c-8ebb-a58409d5c096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247701729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.247701729
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.3271772574
Short name T561
Test name
Test status
Simulation time 325471975 ps
CPU time 3.25 seconds
Started May 30 02:32:12 PM PDT 24
Finished May 30 02:32:17 PM PDT 24
Peak memory 196692 kb
Host smart-5c76c0af-216f-455b-a8e4-d3895533903a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271772574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.3271772574
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.1853096005
Short name T208
Test name
Test status
Simulation time 175102776 ps
CPU time 0.76 seconds
Started May 30 02:32:11 PM PDT 24
Finished May 30 02:32:14 PM PDT 24
Peak memory 195856 kb
Host smart-a3f28867-790e-4ffc-9a2e-bbaf8467fe46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853096005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.1853096005
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.738119926
Short name T605
Test name
Test status
Simulation time 33486412 ps
CPU time 0.98 seconds
Started May 30 02:32:13 PM PDT 24
Finished May 30 02:32:16 PM PDT 24
Peak memory 196156 kb
Host smart-0f8e61c6-0298-42d9-821a-abda48aeb40a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738119926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.738119926
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.1397837000
Short name T617
Test name
Test status
Simulation time 305097540 ps
CPU time 2.95 seconds
Started May 30 02:32:13 PM PDT 24
Finished May 30 02:32:19 PM PDT 24
Peak memory 197904 kb
Host smart-def46f7b-4100-435e-82e3-b6bc893a3b0c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397837000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.1397837000
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.3515765412
Short name T230
Test name
Test status
Simulation time 115460683 ps
CPU time 3.3 seconds
Started May 30 02:32:13 PM PDT 24
Finished May 30 02:32:19 PM PDT 24
Peak memory 197412 kb
Host smart-f40a0056-1aa4-42dd-b3fd-a3e99c70bc92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515765412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.3515765412
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.1792281148
Short name T335
Test name
Test status
Simulation time 44594810 ps
CPU time 0.72 seconds
Started May 30 02:32:11 PM PDT 24
Finished May 30 02:32:13 PM PDT 24
Peak memory 195412 kb
Host smart-c84898fd-79b2-41a0-b876-c165cac5d414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792281148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.1792281148
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.295452972
Short name T642
Test name
Test status
Simulation time 20856697 ps
CPU time 0.8 seconds
Started May 30 02:32:11 PM PDT 24
Finished May 30 02:32:14 PM PDT 24
Peak memory 195644 kb
Host smart-01c0b9b6-c55e-4ca9-b12a-715c2a42a3d4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295452972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullup
_pulldown.295452972
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.846018677
Short name T673
Test name
Test status
Simulation time 368012371 ps
CPU time 4.42 seconds
Started May 30 02:32:14 PM PDT 24
Finished May 30 02:32:20 PM PDT 24
Peak memory 197768 kb
Host smart-639f80d2-3103-4548-8719-972e631d9b57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846018677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ran
dom_long_reg_writes_reg_reads.846018677
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.2161153026
Short name T203
Test name
Test status
Simulation time 35131519 ps
CPU time 1 seconds
Started May 30 02:32:14 PM PDT 24
Finished May 30 02:32:17 PM PDT 24
Peak memory 195632 kb
Host smart-6b84fb70-9f4c-4b0f-96ed-9e80689637f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161153026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.2161153026
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.4266341478
Short name T134
Test name
Test status
Simulation time 244000460 ps
CPU time 1.35 seconds
Started May 30 02:32:08 PM PDT 24
Finished May 30 02:32:10 PM PDT 24
Peak memory 196544 kb
Host smart-72ffdd1c-814f-4773-86dd-33fa04e5e2fa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266341478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.4266341478
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.885356079
Short name T142
Test name
Test status
Simulation time 6258972090 ps
CPU time 155.39 seconds
Started May 30 02:32:11 PM PDT 24
Finished May 30 02:34:47 PM PDT 24
Peak memory 198196 kb
Host smart-b39d3882-58f0-41a2-8471-6ab3337ac8e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885356079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.g
pio_stress_all.885356079
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.2863374827
Short name T237
Test name
Test status
Simulation time 11359534 ps
CPU time 0.57 seconds
Started May 30 02:32:12 PM PDT 24
Finished May 30 02:32:14 PM PDT 24
Peak memory 192556 kb
Host smart-34af6560-f2b2-4a24-b745-d734b4d3409c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863374827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2863374827
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.448073572
Short name T531
Test name
Test status
Simulation time 52079780 ps
CPU time 0.75 seconds
Started May 30 02:32:13 PM PDT 24
Finished May 30 02:32:15 PM PDT 24
Peak memory 195300 kb
Host smart-f7007e70-3966-490a-9b5d-e08157228623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448073572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.448073572
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.521966574
Short name T555
Test name
Test status
Simulation time 1734165260 ps
CPU time 13.29 seconds
Started May 30 02:32:09 PM PDT 24
Finished May 30 02:32:23 PM PDT 24
Peak memory 196984 kb
Host smart-8b3f637f-fd54-489d-9b5b-65b3d5b18ff4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521966574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stres
s.521966574
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.2492890895
Short name T22
Test name
Test status
Simulation time 45031650 ps
CPU time 0.73 seconds
Started May 30 02:32:13 PM PDT 24
Finished May 30 02:32:16 PM PDT 24
Peak memory 194776 kb
Host smart-0746dd72-6ae3-42bd-b3b2-44b7c9804273
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492890895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.2492890895
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.402648509
Short name T299
Test name
Test status
Simulation time 91509438 ps
CPU time 1.17 seconds
Started May 30 02:32:12 PM PDT 24
Finished May 30 02:32:15 PM PDT 24
Peak memory 196024 kb
Host smart-7caba121-c066-4388-9afd-ea0528266486
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402648509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.402648509
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.3523511569
Short name T430
Test name
Test status
Simulation time 123082815 ps
CPU time 2.11 seconds
Started May 30 02:32:09 PM PDT 24
Finished May 30 02:32:12 PM PDT 24
Peak memory 198172 kb
Host smart-16d42328-1541-4482-8ebb-f22f5d62a017
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523511569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.3523511569
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.2198804248
Short name T239
Test name
Test status
Simulation time 167279524 ps
CPU time 3.5 seconds
Started May 30 02:32:11 PM PDT 24
Finished May 30 02:32:16 PM PDT 24
Peak memory 197368 kb
Host smart-c9fba7b9-1b14-4777-9c20-6b89c697fd12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198804248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.2198804248
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.1445081658
Short name T658
Test name
Test status
Simulation time 42629692 ps
CPU time 1.11 seconds
Started May 30 02:32:10 PM PDT 24
Finished May 30 02:32:12 PM PDT 24
Peak memory 195956 kb
Host smart-d060e487-7773-4489-aeeb-cfe29eb98135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445081658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.1445081658
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.3712625684
Short name T323
Test name
Test status
Simulation time 339249820 ps
CPU time 1.33 seconds
Started May 30 02:32:13 PM PDT 24
Finished May 30 02:32:17 PM PDT 24
Peak memory 197088 kb
Host smart-e5d6519c-bc42-472e-9a28-3d2a6616a4e1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712625684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.3712625684
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.1841697096
Short name T325
Test name
Test status
Simulation time 142293824 ps
CPU time 1.43 seconds
Started May 30 02:32:13 PM PDT 24
Finished May 30 02:32:16 PM PDT 24
Peak memory 198044 kb
Host smart-23c82e28-48b4-4a52-97a4-926e0f56a29c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841697096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.1841697096
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.2313972498
Short name T593
Test name
Test status
Simulation time 72755531 ps
CPU time 0.91 seconds
Started May 30 02:32:14 PM PDT 24
Finished May 30 02:32:17 PM PDT 24
Peak memory 195352 kb
Host smart-15f2a001-ebdd-470f-b590-62f2cd838942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313972498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.2313972498
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.3079100688
Short name T589
Test name
Test status
Simulation time 70179481 ps
CPU time 1.05 seconds
Started May 30 02:32:12 PM PDT 24
Finished May 30 02:32:15 PM PDT 24
Peak memory 196300 kb
Host smart-e763e3a6-c686-4d94-af06-85fa6e95b1ab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079100688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.3079100688
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.3858567116
Short name T363
Test name
Test status
Simulation time 51794289241 ps
CPU time 194.41 seconds
Started May 30 02:32:10 PM PDT 24
Finished May 30 02:35:26 PM PDT 24
Peak memory 198248 kb
Host smart-faab9e93-5642-41ce-8866-3056761e528e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858567116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.3858567116
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.4243110761
Short name T266
Test name
Test status
Simulation time 66329418 ps
CPU time 0.56 seconds
Started May 30 02:32:13 PM PDT 24
Finished May 30 02:32:15 PM PDT 24
Peak memory 193836 kb
Host smart-d397ad97-2608-40e4-afaa-0306aab58fce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243110761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.4243110761
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.2331063269
Short name T543
Test name
Test status
Simulation time 51811459 ps
CPU time 0.98 seconds
Started May 30 02:32:12 PM PDT 24
Finished May 30 02:32:15 PM PDT 24
Peak memory 196640 kb
Host smart-bf1fec04-fffe-4baa-986d-1960f14dd271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331063269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.2331063269
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.3934122618
Short name T515
Test name
Test status
Simulation time 1607385767 ps
CPU time 22.56 seconds
Started May 30 02:32:11 PM PDT 24
Finished May 30 02:32:36 PM PDT 24
Peak memory 195604 kb
Host smart-291daa16-e66c-4951-be3e-33a87652e690
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934122618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.3934122618
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.4030026739
Short name T704
Test name
Test status
Simulation time 50299633 ps
CPU time 0.81 seconds
Started May 30 02:32:14 PM PDT 24
Finished May 30 02:32:17 PM PDT 24
Peak memory 196828 kb
Host smart-841845b4-816c-4bc1-8fb5-0ceecd26f9f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030026739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.4030026739
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.1976501234
Short name T412
Test name
Test status
Simulation time 322420737 ps
CPU time 1.17 seconds
Started May 30 02:32:11 PM PDT 24
Finished May 30 02:32:14 PM PDT 24
Peak memory 196944 kb
Host smart-22c2a2b9-3aa1-47ff-b3ee-ec29367c1a1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976501234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.1976501234
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.1943499649
Short name T530
Test name
Test status
Simulation time 95231187 ps
CPU time 2.75 seconds
Started May 30 02:32:13 PM PDT 24
Finished May 30 02:32:17 PM PDT 24
Peak memory 196424 kb
Host smart-75dfcee7-25d0-42ad-8476-7e88ba813c9c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943499649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.1943499649
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.4084123678
Short name T195
Test name
Test status
Simulation time 97407294 ps
CPU time 2.34 seconds
Started May 30 02:32:11 PM PDT 24
Finished May 30 02:32:15 PM PDT 24
Peak memory 197132 kb
Host smart-352756c1-17ba-4b46-a921-917cd494b4cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084123678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.4084123678
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.451237488
Short name T123
Test name
Test status
Simulation time 414750333 ps
CPU time 1.17 seconds
Started May 30 02:32:10 PM PDT 24
Finished May 30 02:32:13 PM PDT 24
Peak memory 196096 kb
Host smart-3cd14fb4-6bba-4518-a7c5-491d3b4df7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451237488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.451237488
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.540119007
Short name T139
Test name
Test status
Simulation time 103710856 ps
CPU time 1.09 seconds
Started May 30 02:32:13 PM PDT 24
Finished May 30 02:32:16 PM PDT 24
Peak memory 196160 kb
Host smart-a82eb604-665a-4ba0-b42b-3b0d54a52b4d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540119007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullup
_pulldown.540119007
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.2506829293
Short name T636
Test name
Test status
Simulation time 172504229 ps
CPU time 3.19 seconds
Started May 30 02:32:15 PM PDT 24
Finished May 30 02:32:20 PM PDT 24
Peak memory 197832 kb
Host smart-673722bf-ab3c-47fb-bc0f-d95d93cebfdb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506829293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.2506829293
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.1196723032
Short name T681
Test name
Test status
Simulation time 147859476 ps
CPU time 1.18 seconds
Started May 30 02:32:14 PM PDT 24
Finished May 30 02:32:17 PM PDT 24
Peak memory 195548 kb
Host smart-36e87669-96f4-4665-b398-84fe28008731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196723032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.1196723032
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.2159352632
Short name T224
Test name
Test status
Simulation time 278918522 ps
CPU time 1.05 seconds
Started May 30 02:32:11 PM PDT 24
Finished May 30 02:32:14 PM PDT 24
Peak memory 195856 kb
Host smart-3695d4ca-f563-43c2-920b-09b98c047c8f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159352632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.2159352632
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.3925368891
Short name T19
Test name
Test status
Simulation time 5417767053 ps
CPU time 29.98 seconds
Started May 30 02:32:15 PM PDT 24
Finished May 30 02:32:46 PM PDT 24
Peak memory 198244 kb
Host smart-aa1d8440-4d0a-422b-ad70-384df23e7721
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925368891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.3925368891
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.985796507
Short name T607
Test name
Test status
Simulation time 90687526 ps
CPU time 0.57 seconds
Started May 30 02:30:55 PM PDT 24
Finished May 30 02:30:57 PM PDT 24
Peak memory 194632 kb
Host smart-2cf4295d-00a9-4147-9768-cd6e03d8f251
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985796507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.985796507
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.893144102
Short name T504
Test name
Test status
Simulation time 148870707 ps
CPU time 0.95 seconds
Started May 30 02:30:55 PM PDT 24
Finished May 30 02:30:57 PM PDT 24
Peak memory 196136 kb
Host smart-35854e79-45ac-4d87-b7be-fb1da862ccd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893144102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.893144102
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.439861421
Short name T246
Test name
Test status
Simulation time 978367093 ps
CPU time 26.11 seconds
Started May 30 02:30:56 PM PDT 24
Finished May 30 02:31:23 PM PDT 24
Peak memory 198016 kb
Host smart-95e613ce-66a4-429d-a478-05c4f30be6ad
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439861421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stress
.439861421
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.4023069473
Short name T4
Test name
Test status
Simulation time 33049900 ps
CPU time 0.67 seconds
Started May 30 02:30:51 PM PDT 24
Finished May 30 02:30:54 PM PDT 24
Peak memory 194732 kb
Host smart-895342e6-ae2b-4060-b1cd-defb571a66e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023069473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.4023069473
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.3394521602
Short name T360
Test name
Test status
Simulation time 357834669 ps
CPU time 1.4 seconds
Started May 30 02:30:56 PM PDT 24
Finished May 30 02:30:59 PM PDT 24
Peak memory 196352 kb
Host smart-6f10abf0-7725-4281-bb8e-49de54eb5bb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394521602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.3394521602
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.1758378500
Short name T213
Test name
Test status
Simulation time 339138507 ps
CPU time 3.42 seconds
Started May 30 02:30:52 PM PDT 24
Finished May 30 02:30:57 PM PDT 24
Peak memory 198020 kb
Host smart-d145261b-5fb6-42ff-8538-8a6979b7fd6c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758378500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.1758378500
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.2473229323
Short name T294
Test name
Test status
Simulation time 115039763 ps
CPU time 2.79 seconds
Started May 30 02:30:59 PM PDT 24
Finished May 30 02:31:02 PM PDT 24
Peak memory 197028 kb
Host smart-de476c05-6270-4daf-b4d6-ea6712733ae9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473229323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
2473229323
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.453499909
Short name T162
Test name
Test status
Simulation time 31620795 ps
CPU time 1.16 seconds
Started May 30 02:30:55 PM PDT 24
Finished May 30 02:30:57 PM PDT 24
Peak memory 195888 kb
Host smart-250332d2-9aef-4147-b87a-c78ceb4041f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453499909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.453499909
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2879944289
Short name T114
Test name
Test status
Simulation time 82093037 ps
CPU time 0.94 seconds
Started May 30 02:30:55 PM PDT 24
Finished May 30 02:30:58 PM PDT 24
Peak memory 196168 kb
Host smart-8e46c076-fd0e-4716-85d1-23bce1da1fbf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879944289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.2879944289
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.1560336052
Short name T693
Test name
Test status
Simulation time 1581469689 ps
CPU time 4.91 seconds
Started May 30 02:30:58 PM PDT 24
Finished May 30 02:31:03 PM PDT 24
Peak memory 198004 kb
Host smart-fd4d133f-0888-4fba-832e-efc6db988684
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560336052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.1560336052
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.1120024080
Short name T43
Test name
Test status
Simulation time 340019424 ps
CPU time 1.03 seconds
Started May 30 02:30:59 PM PDT 24
Finished May 30 02:31:02 PM PDT 24
Peak memory 215028 kb
Host smart-71f446ae-8850-4195-b065-c70d8dfb8669
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120024080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.1120024080
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.664635796
Short name T667
Test name
Test status
Simulation time 121041508 ps
CPU time 1.29 seconds
Started May 30 02:30:59 PM PDT 24
Finished May 30 02:31:02 PM PDT 24
Peak memory 195772 kb
Host smart-26c93f39-fea5-4f1f-967e-2c2e9cb35f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664635796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.664635796
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.3695683463
Short name T316
Test name
Test status
Simulation time 243149400 ps
CPU time 1.33 seconds
Started May 30 02:30:53 PM PDT 24
Finished May 30 02:30:56 PM PDT 24
Peak memory 196876 kb
Host smart-483e6efe-e6fa-47f8-97f3-fa4ab969c593
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695683463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.3695683463
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.3854529125
Short name T106
Test name
Test status
Simulation time 13134771680 ps
CPU time 99.76 seconds
Started May 30 02:31:00 PM PDT 24
Finished May 30 02:32:41 PM PDT 24
Peak memory 198212 kb
Host smart-4508d7a4-cacb-489d-8638-57addd04d3aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854529125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.3854529125
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.1271817638
Short name T71
Test name
Test status
Simulation time 203621044403 ps
CPU time 2120.46 seconds
Started May 30 02:30:55 PM PDT 24
Finished May 30 03:06:17 PM PDT 24
Peak memory 198288 kb
Host smart-f0c2e1af-36aa-47cc-aca0-a1188f19f197
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1271817638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.1271817638
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.3683227303
Short name T550
Test name
Test status
Simulation time 22715679 ps
CPU time 0.56 seconds
Started May 30 02:32:31 PM PDT 24
Finished May 30 02:32:33 PM PDT 24
Peak memory 194620 kb
Host smart-b00ea28e-35a5-4062-8eff-d8933f79f619
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683227303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.3683227303
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.2938337548
Short name T130
Test name
Test status
Simulation time 394202776 ps
CPU time 0.84 seconds
Started May 30 02:32:15 PM PDT 24
Finished May 30 02:32:17 PM PDT 24
Peak memory 195528 kb
Host smart-bc253c46-b679-400f-94be-68559308123b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938337548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.2938337548
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.2274330387
Short name T448
Test name
Test status
Simulation time 517133562 ps
CPU time 19.26 seconds
Started May 30 02:32:22 PM PDT 24
Finished May 30 02:32:42 PM PDT 24
Peak memory 197040 kb
Host smart-bfbcf33c-aa70-42c9-99b5-fc60f950313f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274330387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.2274330387
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.3115497649
Short name T630
Test name
Test status
Simulation time 124735788 ps
CPU time 1.08 seconds
Started May 30 02:32:19 PM PDT 24
Finished May 30 02:32:21 PM PDT 24
Peak memory 197920 kb
Host smart-7d448eb5-49ab-46d9-a8b9-5de4f74fbe14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115497649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.3115497649
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.999092085
Short name T209
Test name
Test status
Simulation time 24352848 ps
CPU time 0.82 seconds
Started May 30 02:32:12 PM PDT 24
Finished May 30 02:32:14 PM PDT 24
Peak memory 196324 kb
Host smart-33e08bd0-f54b-449e-b9aa-a874c1fecde5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999092085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.999092085
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.2071791669
Short name T409
Test name
Test status
Simulation time 134444838 ps
CPU time 2.99 seconds
Started May 30 02:32:22 PM PDT 24
Finished May 30 02:32:25 PM PDT 24
Peak memory 198140 kb
Host smart-452d2731-5c8d-4271-b9a7-3e76b403aa13
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071791669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.2071791669
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.1405990164
Short name T148
Test name
Test status
Simulation time 236427724 ps
CPU time 2.74 seconds
Started May 30 02:32:12 PM PDT 24
Finished May 30 02:32:16 PM PDT 24
Peak memory 195792 kb
Host smart-84c81c3b-70a3-415e-82e2-c03c50dfbe47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405990164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.1405990164
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.836494383
Short name T637
Test name
Test status
Simulation time 132941712 ps
CPU time 0.96 seconds
Started May 30 02:32:12 PM PDT 24
Finished May 30 02:32:15 PM PDT 24
Peak memory 196584 kb
Host smart-e50d8d6d-1d14-4d33-b83a-6200af928a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836494383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.836494383
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.3298556262
Short name T18
Test name
Test status
Simulation time 158707572 ps
CPU time 0.96 seconds
Started May 30 02:32:13 PM PDT 24
Finished May 30 02:32:16 PM PDT 24
Peak memory 196108 kb
Host smart-f6ea3f56-9b3a-4006-ad73-f161a80f97f7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298556262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.3298556262
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.3493244977
Short name T388
Test name
Test status
Simulation time 149453963 ps
CPU time 1.54 seconds
Started May 30 02:32:30 PM PDT 24
Finished May 30 02:32:33 PM PDT 24
Peak memory 198060 kb
Host smart-0769327c-8ab6-438a-9ec5-bd92d8b06588
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493244977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.3493244977
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.603058995
Short name T205
Test name
Test status
Simulation time 33479804 ps
CPU time 0.91 seconds
Started May 30 02:32:11 PM PDT 24
Finished May 30 02:32:14 PM PDT 24
Peak memory 196060 kb
Host smart-4df312d1-6cfd-499b-adcb-ee16f0960b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603058995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.603058995
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.3556047932
Short name T318
Test name
Test status
Simulation time 42634959 ps
CPU time 1.2 seconds
Started May 30 02:32:11 PM PDT 24
Finished May 30 02:32:14 PM PDT 24
Peak memory 196556 kb
Host smart-dcf058f1-c5d5-4bba-80da-f659e84400cb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556047932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.3556047932
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.660561636
Short name T370
Test name
Test status
Simulation time 12922568624 ps
CPU time 85.48 seconds
Started May 30 02:32:24 PM PDT 24
Finished May 30 02:33:50 PM PDT 24
Peak memory 197628 kb
Host smart-248e2b26-1c3c-4315-baeb-2eba37090f88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660561636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.g
pio_stress_all.660561636
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.1223728762
Short name T74
Test name
Test status
Simulation time 57456833425 ps
CPU time 1405.12 seconds
Started May 30 02:32:31 PM PDT 24
Finished May 30 02:55:58 PM PDT 24
Peak memory 198224 kb
Host smart-6fef39f2-f3b8-405d-9126-ee4a1998a710
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1223728762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.1223728762
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.269015935
Short name T527
Test name
Test status
Simulation time 37370072 ps
CPU time 0.59 seconds
Started May 30 02:32:26 PM PDT 24
Finished May 30 02:32:27 PM PDT 24
Peak memory 194144 kb
Host smart-a573d7a8-b5ca-4597-8cbc-be6b9bdcfb17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269015935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.269015935
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.2194917598
Short name T167
Test name
Test status
Simulation time 28023725 ps
CPU time 0.87 seconds
Started May 30 02:32:22 PM PDT 24
Finished May 30 02:32:24 PM PDT 24
Peak memory 197044 kb
Host smart-fbe23a6e-6408-4a26-b8a8-5933c259a3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194917598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.2194917598
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.2441064114
Short name T229
Test name
Test status
Simulation time 732121444 ps
CPU time 13.9 seconds
Started May 30 02:32:24 PM PDT 24
Finished May 30 02:32:38 PM PDT 24
Peak memory 196864 kb
Host smart-2a0e2dc2-f93b-4313-8c1b-c9e1cc057000
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441064114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.2441064114
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.41433346
Short name T535
Test name
Test status
Simulation time 44994116 ps
CPU time 0.81 seconds
Started May 30 02:32:32 PM PDT 24
Finished May 30 02:32:34 PM PDT 24
Peak memory 196004 kb
Host smart-3b5debdd-be9d-4e78-a89d-f65e11f1676c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41433346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.41433346
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.1908272723
Short name T576
Test name
Test status
Simulation time 1233329270 ps
CPU time 1.46 seconds
Started May 30 02:32:30 PM PDT 24
Finished May 30 02:32:33 PM PDT 24
Peak memory 198144 kb
Host smart-51546031-7cec-44ed-a815-45cab47cc1ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908272723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.1908272723
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.343013039
Short name T253
Test name
Test status
Simulation time 74103858 ps
CPU time 2.75 seconds
Started May 30 02:32:25 PM PDT 24
Finished May 30 02:32:29 PM PDT 24
Peak memory 198108 kb
Host smart-fc99bcb0-572a-436e-a7a9-afee229c911d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343013039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.gpio_intr_with_filter_rand_intr_event.343013039
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.3254852534
Short name T595
Test name
Test status
Simulation time 110892780 ps
CPU time 2.62 seconds
Started May 30 02:32:31 PM PDT 24
Finished May 30 02:32:35 PM PDT 24
Peak memory 197268 kb
Host smart-e68c3219-aa13-4ade-a6f2-1d859f2b0359
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254852534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.3254852534
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.2439987592
Short name T124
Test name
Test status
Simulation time 131916516 ps
CPU time 0.99 seconds
Started May 30 02:32:23 PM PDT 24
Finished May 30 02:32:25 PM PDT 24
Peak memory 196036 kb
Host smart-3dda8b7b-301f-48d7-80ec-9dac0da45f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439987592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.2439987592
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.1032734860
Short name T68
Test name
Test status
Simulation time 58026143 ps
CPU time 1.24 seconds
Started May 30 02:32:31 PM PDT 24
Finished May 30 02:32:33 PM PDT 24
Peak memory 196840 kb
Host smart-1e3c8f5a-239a-48d9-b355-f4dc7905f67f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032734860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.1032734860
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.3054016412
Short name T278
Test name
Test status
Simulation time 105485930 ps
CPU time 2.54 seconds
Started May 30 02:32:25 PM PDT 24
Finished May 30 02:32:29 PM PDT 24
Peak memory 198052 kb
Host smart-4c0bf9f9-c41a-4c92-add0-2d87bcd6a0c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054016412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.3054016412
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.762174581
Short name T565
Test name
Test status
Simulation time 50783682 ps
CPU time 0.92 seconds
Started May 30 02:32:27 PM PDT 24
Finished May 30 02:32:29 PM PDT 24
Peak memory 196352 kb
Host smart-007191bc-62cd-4aa2-9d85-23149a1bf637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762174581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.762174581
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.3303509711
Short name T594
Test name
Test status
Simulation time 181051603 ps
CPU time 1.14 seconds
Started May 30 02:32:24 PM PDT 24
Finished May 30 02:32:26 PM PDT 24
Peak memory 195212 kb
Host smart-63243481-5c55-4f79-a352-28fe0a2d92fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303509711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.3303509711
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.3387992412
Short name T472
Test name
Test status
Simulation time 23564336396 ps
CPU time 81.76 seconds
Started May 30 02:32:30 PM PDT 24
Finished May 30 02:33:53 PM PDT 24
Peak memory 198216 kb
Host smart-d40b7c07-29fb-4660-b438-ac62db2d4dd2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387992412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.3387992412
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.3455657071
Short name T597
Test name
Test status
Simulation time 29683213 ps
CPU time 0.57 seconds
Started May 30 02:32:28 PM PDT 24
Finished May 30 02:32:30 PM PDT 24
Peak memory 193528 kb
Host smart-d7d5120b-6ee0-4272-aa94-e249e9d2e8ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455657071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.3455657071
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.3477276538
Short name T718
Test name
Test status
Simulation time 185625695 ps
CPU time 0.91 seconds
Started May 30 02:32:28 PM PDT 24
Finished May 30 02:32:31 PM PDT 24
Peak memory 196848 kb
Host smart-00db0535-347c-443b-a1b3-931fc79be9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477276538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.3477276538
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.2517958189
Short name T507
Test name
Test status
Simulation time 1402563301 ps
CPU time 19.33 seconds
Started May 30 02:32:21 PM PDT 24
Finished May 30 02:32:41 PM PDT 24
Peak memory 196972 kb
Host smart-d3ffe62f-979f-4df9-888c-47125d199238
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517958189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.2517958189
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.3718976686
Short name T261
Test name
Test status
Simulation time 79423334 ps
CPU time 0.76 seconds
Started May 30 02:32:25 PM PDT 24
Finished May 30 02:32:27 PM PDT 24
Peak memory 195832 kb
Host smart-13a6b1bc-24f8-4ca5-80f3-8cb06d2cb599
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718976686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3718976686
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.2277540109
Short name T171
Test name
Test status
Simulation time 61242356 ps
CPU time 1.04 seconds
Started May 30 02:32:25 PM PDT 24
Finished May 30 02:32:27 PM PDT 24
Peak memory 196048 kb
Host smart-5f12217c-9ff5-4940-8189-207574452726
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277540109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.2277540109
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.2808297697
Short name T714
Test name
Test status
Simulation time 48872923 ps
CPU time 2.09 seconds
Started May 30 02:32:22 PM PDT 24
Finished May 30 02:32:26 PM PDT 24
Peak memory 198160 kb
Host smart-0cc20c33-8dda-4d12-bf3c-ff4479f31280
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808297697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.2808297697
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.245290322
Short name T698
Test name
Test status
Simulation time 117498164 ps
CPU time 3.36 seconds
Started May 30 02:32:31 PM PDT 24
Finished May 30 02:32:36 PM PDT 24
Peak memory 198080 kb
Host smart-b7c7dacd-f46f-45e2-905f-73bbb4f2f36a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245290322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger.
245290322
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.987528850
Short name T79
Test name
Test status
Simulation time 29684015 ps
CPU time 1.11 seconds
Started May 30 02:32:21 PM PDT 24
Finished May 30 02:32:23 PM PDT 24
Peak memory 196188 kb
Host smart-10bb8495-ad54-4b20-b793-0389727ec0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987528850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.987528850
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.3305574270
Short name T542
Test name
Test status
Simulation time 80016629 ps
CPU time 0.99 seconds
Started May 30 02:32:22 PM PDT 24
Finished May 30 02:32:25 PM PDT 24
Peak memory 196048 kb
Host smart-c08b327e-cd97-4412-9888-35b5e9797692
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305574270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.3305574270
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.1613942480
Short name T453
Test name
Test status
Simulation time 3336453084 ps
CPU time 3.42 seconds
Started May 30 02:32:30 PM PDT 24
Finished May 30 02:32:35 PM PDT 24
Peak memory 198204 kb
Host smart-e11104ea-7f5a-45c1-82f5-10e80a13dfb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613942480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.1613942480
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.548448834
Short name T663
Test name
Test status
Simulation time 82857990 ps
CPU time 1.15 seconds
Started May 30 02:32:25 PM PDT 24
Finished May 30 02:32:27 PM PDT 24
Peak memory 196324 kb
Host smart-c6914e38-155d-42cd-8f26-b8f08483bf68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548448834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.548448834
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.2915665476
Short name T275
Test name
Test status
Simulation time 88424868 ps
CPU time 1.47 seconds
Started May 30 02:32:25 PM PDT 24
Finished May 30 02:32:28 PM PDT 24
Peak memory 196756 kb
Host smart-0cc7a759-f85c-4b89-89a2-f2d899926082
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915665476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.2915665476
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.1553724980
Short name T659
Test name
Test status
Simulation time 10055226955 ps
CPU time 106.9 seconds
Started May 30 02:32:26 PM PDT 24
Finished May 30 02:34:14 PM PDT 24
Peak memory 198216 kb
Host smart-92292ed1-805a-478c-9d8b-4ab27413a3f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553724980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.1553724980
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.1809077045
Short name T450
Test name
Test status
Simulation time 46679778 ps
CPU time 0.6 seconds
Started May 30 02:32:31 PM PDT 24
Finished May 30 02:32:33 PM PDT 24
Peak memory 193968 kb
Host smart-784a3884-3fc5-4c6f-a9f5-f95c8a75e3cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809077045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.1809077045
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.3188214648
Short name T653
Test name
Test status
Simulation time 66942430 ps
CPU time 0.74 seconds
Started May 30 02:32:31 PM PDT 24
Finished May 30 02:32:34 PM PDT 24
Peak memory 195300 kb
Host smart-8dd9be02-2a03-45ba-9cad-62d64d8e01b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188214648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.3188214648
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.816257502
Short name T129
Test name
Test status
Simulation time 817770439 ps
CPU time 22.77 seconds
Started May 30 02:32:22 PM PDT 24
Finished May 30 02:32:46 PM PDT 24
Peak memory 197020 kb
Host smart-41dcb25a-f530-454b-8350-73e3699bda26
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816257502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stres
s.816257502
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.2691647700
Short name T367
Test name
Test status
Simulation time 79574423 ps
CPU time 0.96 seconds
Started May 30 02:32:26 PM PDT 24
Finished May 30 02:32:28 PM PDT 24
Peak memory 196652 kb
Host smart-108c1204-bcce-467f-8842-1e0934fd7496
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691647700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.2691647700
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.1383226458
Short name T153
Test name
Test status
Simulation time 69570146 ps
CPU time 1.31 seconds
Started May 30 02:32:19 PM PDT 24
Finished May 30 02:32:21 PM PDT 24
Peak memory 196264 kb
Host smart-56828c7d-9489-4179-8164-dea817445593
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383226458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.1383226458
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.3526587119
Short name T186
Test name
Test status
Simulation time 41478210 ps
CPU time 1.7 seconds
Started May 30 02:32:32 PM PDT 24
Finished May 30 02:32:35 PM PDT 24
Peak memory 198068 kb
Host smart-b7a60175-feaa-4b3b-88d1-423e838f3c35
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526587119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.3526587119
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.2415900182
Short name T688
Test name
Test status
Simulation time 710853053 ps
CPU time 3.49 seconds
Started May 30 02:32:23 PM PDT 24
Finished May 30 02:32:28 PM PDT 24
Peak memory 196928 kb
Host smart-2a62522d-3943-4263-b916-50c291ce8010
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415900182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.2415900182
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.294995612
Short name T69
Test name
Test status
Simulation time 598868734 ps
CPU time 1.24 seconds
Started May 30 02:32:23 PM PDT 24
Finished May 30 02:32:26 PM PDT 24
Peak memory 196648 kb
Host smart-368ccc6d-aa0d-4158-a433-d5f51584d247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294995612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.294995612
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.1859764066
Short name T538
Test name
Test status
Simulation time 21040443 ps
CPU time 0.9 seconds
Started May 30 02:32:25 PM PDT 24
Finished May 30 02:32:27 PM PDT 24
Peak memory 196632 kb
Host smart-a8b5e59b-ea12-44b3-a8aa-35a6dcf5ee3c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859764066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.1859764066
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.573514503
Short name T243
Test name
Test status
Simulation time 96667736 ps
CPU time 4.4 seconds
Started May 30 02:32:26 PM PDT 24
Finished May 30 02:32:31 PM PDT 24
Peak memory 198068 kb
Host smart-ba45ff5a-30e4-48df-9874-a11c96755422
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573514503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ran
dom_long_reg_writes_reg_reads.573514503
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.4067577739
Short name T654
Test name
Test status
Simulation time 83019451 ps
CPU time 1.37 seconds
Started May 30 02:32:20 PM PDT 24
Finished May 30 02:32:22 PM PDT 24
Peak memory 196660 kb
Host smart-cc94e8f6-593f-48f4-9ad1-b410a5837b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067577739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.4067577739
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.1679081217
Short name T574
Test name
Test status
Simulation time 124258283 ps
CPU time 0.92 seconds
Started May 30 02:32:28 PM PDT 24
Finished May 30 02:32:30 PM PDT 24
Peak memory 196580 kb
Host smart-6e99e91e-1bcd-4990-a383-1be4e22306ce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679081217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.1679081217
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.668973047
Short name T717
Test name
Test status
Simulation time 19072609610 ps
CPU time 32.42 seconds
Started May 30 02:32:31 PM PDT 24
Finished May 30 02:33:05 PM PDT 24
Peak memory 198164 kb
Host smart-dcfa4e68-d3af-44b0-810a-1402df2f243f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668973047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.g
pio_stress_all.668973047
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.969084139
Short name T497
Test name
Test status
Simulation time 75791462618 ps
CPU time 1749.69 seconds
Started May 30 02:32:28 PM PDT 24
Finished May 30 03:01:39 PM PDT 24
Peak memory 198268 kb
Host smart-7fed7701-ee0f-470c-aa8c-96e6f81829ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=969084139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.969084139
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.1395917651
Short name T371
Test name
Test status
Simulation time 12560819 ps
CPU time 0.58 seconds
Started May 30 02:32:22 PM PDT 24
Finished May 30 02:32:24 PM PDT 24
Peak memory 194660 kb
Host smart-c515edb0-b3d8-4802-ad75-2da044d67b67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395917651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.1395917651
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.3045782898
Short name T359
Test name
Test status
Simulation time 109276436 ps
CPU time 0.7 seconds
Started May 30 02:32:29 PM PDT 24
Finished May 30 02:32:31 PM PDT 24
Peak memory 195388 kb
Host smart-5486a1e8-985f-4b39-8186-6bf70a0a07dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045782898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.3045782898
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.1793489560
Short name T689
Test name
Test status
Simulation time 457954006 ps
CPU time 7 seconds
Started May 30 02:32:28 PM PDT 24
Finished May 30 02:32:36 PM PDT 24
Peak memory 196856 kb
Host smart-c410e97f-f5b7-48a0-b3f2-dab9ee6bcfc8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793489560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.1793489560
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.213053659
Short name T108
Test name
Test status
Simulation time 156604955 ps
CPU time 0.98 seconds
Started May 30 02:32:28 PM PDT 24
Finished May 30 02:32:30 PM PDT 24
Peak memory 197848 kb
Host smart-879347cd-8a3d-4b2c-abab-580dadcc6285
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213053659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.213053659
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.3491027674
Short name T147
Test name
Test status
Simulation time 29675872 ps
CPU time 0.76 seconds
Started May 30 02:32:31 PM PDT 24
Finished May 30 02:32:33 PM PDT 24
Peak memory 195468 kb
Host smart-85be8619-2266-48b0-99a5-729cab879aa4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491027674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.3491027674
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.1829626183
Short name T215
Test name
Test status
Simulation time 22905062 ps
CPU time 0.97 seconds
Started May 30 02:32:27 PM PDT 24
Finished May 30 02:32:30 PM PDT 24
Peak memory 197200 kb
Host smart-3baaa8ce-7ddc-4a6d-a6fc-15dbb0f1c581
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829626183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.1829626183
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.303445819
Short name T287
Test name
Test status
Simulation time 230089030 ps
CPU time 3.68 seconds
Started May 30 02:32:27 PM PDT 24
Finished May 30 02:32:32 PM PDT 24
Peak memory 197408 kb
Host smart-008b5adb-8ec1-4096-9558-40411e39ecc4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303445819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger.
303445819
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.3702532041
Short name T676
Test name
Test status
Simulation time 325588126 ps
CPU time 1.12 seconds
Started May 30 02:32:26 PM PDT 24
Finished May 30 02:32:28 PM PDT 24
Peak memory 196660 kb
Host smart-ed24e329-5fb8-42ad-96be-136d0ac57894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702532041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.3702532041
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.4294608603
Short name T436
Test name
Test status
Simulation time 90773086 ps
CPU time 0.82 seconds
Started May 30 02:32:28 PM PDT 24
Finished May 30 02:32:30 PM PDT 24
Peak memory 195528 kb
Host smart-c849fc54-b0c9-498a-bd9a-839e2bb24eec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294608603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.4294608603
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.1612551665
Short name T712
Test name
Test status
Simulation time 726184626 ps
CPU time 3.66 seconds
Started May 30 02:32:22 PM PDT 24
Finished May 30 02:32:26 PM PDT 24
Peak memory 197968 kb
Host smart-7c0f9570-a226-4857-b582-24ff2177077d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612551665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.1612551665
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.3279555209
Short name T255
Test name
Test status
Simulation time 204333504 ps
CPU time 0.92 seconds
Started May 30 02:32:21 PM PDT 24
Finished May 30 02:32:23 PM PDT 24
Peak memory 196180 kb
Host smart-591a0976-3d84-4f04-8451-f7ac45c9a97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279555209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.3279555209
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.1041887863
Short name T127
Test name
Test status
Simulation time 33592097 ps
CPU time 1.07 seconds
Started May 30 02:32:26 PM PDT 24
Finished May 30 02:32:29 PM PDT 24
Peak memory 195804 kb
Host smart-3cdb9135-407b-4d3c-80b6-9ae1d1f48e9b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041887863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.1041887863
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.2849725080
Short name T435
Test name
Test status
Simulation time 25031446758 ps
CPU time 178.96 seconds
Started May 30 02:32:27 PM PDT 24
Finished May 30 02:35:27 PM PDT 24
Peak memory 198292 kb
Host smart-d90b38d3-89fb-4840-83b3-7e9a9d1afd78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849725080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.2849725080
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.2423890331
Short name T669
Test name
Test status
Simulation time 140307351581 ps
CPU time 982.68 seconds
Started May 30 02:32:21 PM PDT 24
Finished May 30 02:48:45 PM PDT 24
Peak memory 198324 kb
Host smart-fee1f616-eaef-4ee3-ab45-dd487736645d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2423890331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.2423890331
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.3249353663
Short name T625
Test name
Test status
Simulation time 41911725 ps
CPU time 0.62 seconds
Started May 30 02:32:21 PM PDT 24
Finished May 30 02:32:23 PM PDT 24
Peak memory 194824 kb
Host smart-fdd5ad8b-6d0d-444a-929c-db916a7b9b3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249353663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.3249353663
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.2121511771
Short name T544
Test name
Test status
Simulation time 51938177 ps
CPU time 0.92 seconds
Started May 30 02:32:27 PM PDT 24
Finished May 30 02:32:30 PM PDT 24
Peak memory 196700 kb
Host smart-6f12d372-870c-4b11-90e7-cbc632586725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121511771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.2121511771
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.2474457291
Short name T399
Test name
Test status
Simulation time 3014062913 ps
CPU time 22.24 seconds
Started May 30 02:32:27 PM PDT 24
Finished May 30 02:32:50 PM PDT 24
Peak memory 195984 kb
Host smart-f84fa278-e342-4267-8879-be36d4b84855
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474457291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.2474457291
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.4147015688
Short name T56
Test name
Test status
Simulation time 188936104 ps
CPU time 1.07 seconds
Started May 30 02:32:30 PM PDT 24
Finished May 30 02:32:32 PM PDT 24
Peak memory 196668 kb
Host smart-e1abd0b4-6a9b-4e89-8fb9-7c06c0e74b40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147015688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.4147015688
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.1325885990
Short name T392
Test name
Test status
Simulation time 23606266 ps
CPU time 0.78 seconds
Started May 30 02:32:27 PM PDT 24
Finished May 30 02:32:29 PM PDT 24
Peak memory 196360 kb
Host smart-44e6fd06-3c94-4f21-82b4-15bf76f8cd08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325885990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.1325885990
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.1844025017
Short name T492
Test name
Test status
Simulation time 67373587 ps
CPU time 1.63 seconds
Started May 30 02:32:30 PM PDT 24
Finished May 30 02:32:33 PM PDT 24
Peak memory 196368 kb
Host smart-3620aede-30d8-4f06-b43f-bdd3b85d526a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844025017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.1844025017
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.2216806317
Short name T481
Test name
Test status
Simulation time 313374708 ps
CPU time 1.98 seconds
Started May 30 02:32:22 PM PDT 24
Finished May 30 02:32:25 PM PDT 24
Peak memory 195920 kb
Host smart-60349362-695d-4fc2-bc61-8f6d4be86038
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216806317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.2216806317
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.2500825817
Short name T390
Test name
Test status
Simulation time 75590367 ps
CPU time 0.88 seconds
Started May 30 02:32:30 PM PDT 24
Finished May 30 02:32:32 PM PDT 24
Peak memory 196012 kb
Host smart-36d616c7-5d42-44c1-9cb9-7f101c84634b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500825817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.2500825817
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.189581202
Short name T638
Test name
Test status
Simulation time 208888137 ps
CPU time 1.04 seconds
Started May 30 02:32:29 PM PDT 24
Finished May 30 02:32:31 PM PDT 24
Peak memory 196124 kb
Host smart-cd3d3502-35b3-4140-8fd8-e06be1671faf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189581202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullup
_pulldown.189581202
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.2917579016
Short name T387
Test name
Test status
Simulation time 38123556 ps
CPU time 1.68 seconds
Started May 30 02:32:27 PM PDT 24
Finished May 30 02:32:31 PM PDT 24
Peak memory 198040 kb
Host smart-3587788e-0248-4fc7-8a4b-e25a20486638
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917579016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.2917579016
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.1375780988
Short name T661
Test name
Test status
Simulation time 181360660 ps
CPU time 1.04 seconds
Started May 30 02:32:22 PM PDT 24
Finished May 30 02:32:25 PM PDT 24
Peak memory 196256 kb
Host smart-c8dc16e7-5b98-42ab-890c-15672d9cee0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375780988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.1375780988
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.1356847954
Short name T23
Test name
Test status
Simulation time 115043844 ps
CPU time 0.86 seconds
Started May 30 02:32:23 PM PDT 24
Finished May 30 02:32:25 PM PDT 24
Peak memory 195368 kb
Host smart-1531efda-2db1-4169-a56c-93830ff5b214
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356847954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.1356847954
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.720304172
Short name T329
Test name
Test status
Simulation time 37119210903 ps
CPU time 115.12 seconds
Started May 30 02:32:27 PM PDT 24
Finished May 30 02:34:24 PM PDT 24
Peak memory 198148 kb
Host smart-31dc3eb2-b4aa-4964-b897-76b9da2e0e1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720304172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.g
pio_stress_all.720304172
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.1242786295
Short name T277
Test name
Test status
Simulation time 16097205 ps
CPU time 0.58 seconds
Started May 30 02:32:43 PM PDT 24
Finished May 30 02:32:45 PM PDT 24
Peak memory 194112 kb
Host smart-25edabbf-7946-40dd-ab24-66ac90d62e33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242786295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.1242786295
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.3299404683
Short name T315
Test name
Test status
Simulation time 26155016 ps
CPU time 0.71 seconds
Started May 30 02:32:30 PM PDT 24
Finished May 30 02:32:32 PM PDT 24
Peak memory 195100 kb
Host smart-097f63c9-1224-4951-b7e6-cca6fb18ba3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299404683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.3299404683
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.4051490171
Short name T549
Test name
Test status
Simulation time 1046634426 ps
CPU time 5.73 seconds
Started May 30 02:32:36 PM PDT 24
Finished May 30 02:32:44 PM PDT 24
Peak memory 196812 kb
Host smart-0d96e21c-d2b2-4407-b403-f98d8b7c7141
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051490171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.4051490171
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.422241849
Short name T473
Test name
Test status
Simulation time 44846173 ps
CPU time 0.68 seconds
Started May 30 02:32:32 PM PDT 24
Finished May 30 02:32:35 PM PDT 24
Peak memory 195608 kb
Host smart-57536890-6712-4ed6-865c-65f503ca64a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422241849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.422241849
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.3951992584
Short name T221
Test name
Test status
Simulation time 79822978 ps
CPU time 1.25 seconds
Started May 30 02:32:37 PM PDT 24
Finished May 30 02:32:41 PM PDT 24
Peak memory 196708 kb
Host smart-f5d79146-2771-4b59-aa2a-9e7b4d454303
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951992584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.3951992584
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.777776161
Short name T692
Test name
Test status
Simulation time 63260352 ps
CPU time 2.63 seconds
Started May 30 02:32:37 PM PDT 24
Finished May 30 02:32:42 PM PDT 24
Peak memory 198140 kb
Host smart-2f6cf0bd-27ea-4b55-9108-5937da437475
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777776161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.gpio_intr_with_filter_rand_intr_event.777776161
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.4113388989
Short name T604
Test name
Test status
Simulation time 306667962 ps
CPU time 2.99 seconds
Started May 30 02:32:32 PM PDT 24
Finished May 30 02:32:36 PM PDT 24
Peak memory 197244 kb
Host smart-903a5f82-7a5b-4b95-ae02-be94a07223cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113388989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.4113388989
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.3156736008
Short name T578
Test name
Test status
Simulation time 104289660 ps
CPU time 1.08 seconds
Started May 30 02:32:34 PM PDT 24
Finished May 30 02:32:37 PM PDT 24
Peak memory 196100 kb
Host smart-5b4e2f52-14cd-441a-bb6a-174623706aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156736008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.3156736008
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.3569723136
Short name T176
Test name
Test status
Simulation time 64847303 ps
CPU time 1.01 seconds
Started May 30 02:32:36 PM PDT 24
Finished May 30 02:32:40 PM PDT 24
Peak memory 196564 kb
Host smart-cb47e02d-e114-43fe-aa28-20d617e6bde2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569723136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.3569723136
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.3402269840
Short name T570
Test name
Test status
Simulation time 224597127 ps
CPU time 2.32 seconds
Started May 30 02:32:33 PM PDT 24
Finished May 30 02:32:38 PM PDT 24
Peak memory 198032 kb
Host smart-fd0fa504-f0e3-4279-a679-66742fb83a09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402269840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.3402269840
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.1173229440
Short name T225
Test name
Test status
Simulation time 138575362 ps
CPU time 1.28 seconds
Started May 30 02:32:36 PM PDT 24
Finished May 30 02:32:40 PM PDT 24
Peak memory 195612 kb
Host smart-725e0c73-20f2-4351-a75b-a2f6637ce323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173229440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.1173229440
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.2853570683
Short name T121
Test name
Test status
Simulation time 216473543 ps
CPU time 1.31 seconds
Started May 30 02:32:36 PM PDT 24
Finished May 30 02:32:41 PM PDT 24
Peak memory 196788 kb
Host smart-81907e6a-79e1-49eb-815f-4c7ba163086c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853570683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.2853570683
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.69172651
Short name T376
Test name
Test status
Simulation time 4744743774 ps
CPU time 100.76 seconds
Started May 30 02:32:36 PM PDT 24
Finished May 30 02:34:20 PM PDT 24
Peak memory 198204 kb
Host smart-864feb09-8bf3-460e-a768-d7147e1e73ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69172651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gp
io_stress_all.69172651
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.1835393974
Short name T297
Test name
Test status
Simulation time 12939091 ps
CPU time 0.6 seconds
Started May 30 02:32:33 PM PDT 24
Finished May 30 02:32:36 PM PDT 24
Peak memory 193936 kb
Host smart-1e1ea4e0-9ad4-423a-84bf-2d036ce663f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835393974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.1835393974
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.3365207879
Short name T317
Test name
Test status
Simulation time 219086709 ps
CPU time 0.64 seconds
Started May 30 02:32:35 PM PDT 24
Finished May 30 02:32:39 PM PDT 24
Peak memory 193956 kb
Host smart-2ad3a610-f7a3-45c3-8d18-739feb316c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365207879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.3365207879
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.3088195875
Short name T289
Test name
Test status
Simulation time 735690844 ps
CPU time 24.34 seconds
Started May 30 02:32:36 PM PDT 24
Finished May 30 02:33:03 PM PDT 24
Peak memory 196704 kb
Host smart-1b5bf6c6-9a93-406a-8214-4fe2fd0a3b75
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088195875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.3088195875
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.139977539
Short name T358
Test name
Test status
Simulation time 94130249 ps
CPU time 0.76 seconds
Started May 30 02:32:33 PM PDT 24
Finished May 30 02:32:36 PM PDT 24
Peak memory 195860 kb
Host smart-b0e75342-834f-4799-b7d8-004949260153
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139977539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.139977539
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.2759923974
Short name T512
Test name
Test status
Simulation time 47456702 ps
CPU time 1.28 seconds
Started May 30 02:32:33 PM PDT 24
Finished May 30 02:32:37 PM PDT 24
Peak memory 197028 kb
Host smart-5345f87c-53b1-4a1b-9892-e6d8621dc8fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759923974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.2759923974
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.2771777380
Short name T303
Test name
Test status
Simulation time 147818717 ps
CPU time 1.44 seconds
Started May 30 02:32:34 PM PDT 24
Finished May 30 02:32:37 PM PDT 24
Peak memory 196116 kb
Host smart-71436477-57a4-4a07-ad60-ef691e245af6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771777380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.2771777380
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.661493793
Short name T179
Test name
Test status
Simulation time 29030321 ps
CPU time 0.84 seconds
Started May 30 02:32:36 PM PDT 24
Finished May 30 02:32:40 PM PDT 24
Peak memory 196340 kb
Host smart-ee5e460b-8b76-4fda-bb71-d3ea3169f95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661493793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.661493793
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.1808354148
Short name T251
Test name
Test status
Simulation time 20007109 ps
CPU time 0.73 seconds
Started May 30 02:32:32 PM PDT 24
Finished May 30 02:32:35 PM PDT 24
Peak memory 194364 kb
Host smart-4a4c7bca-fdee-48ae-9507-b77c759c43f6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808354148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.1808354148
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.2787555132
Short name T45
Test name
Test status
Simulation time 524675522 ps
CPU time 4.54 seconds
Started May 30 02:32:35 PM PDT 24
Finished May 30 02:32:42 PM PDT 24
Peak memory 197904 kb
Host smart-a4f9118b-467d-4e8e-b5b0-f273f7e023f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787555132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.2787555132
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.221473383
Short name T699
Test name
Test status
Simulation time 175227038 ps
CPU time 1.21 seconds
Started May 30 02:32:35 PM PDT 24
Finished May 30 02:32:39 PM PDT 24
Peak memory 197912 kb
Host smart-b8ddd91f-4a40-4771-9ddb-5ab5331b4cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221473383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.221473383
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.2354854316
Short name T581
Test name
Test status
Simulation time 44183563 ps
CPU time 1.28 seconds
Started May 30 02:32:38 PM PDT 24
Finished May 30 02:32:41 PM PDT 24
Peak memory 195556 kb
Host smart-648e0bc2-7632-40c3-aa87-ea5c19fb986b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354854316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.2354854316
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.1822438572
Short name T425
Test name
Test status
Simulation time 13802886273 ps
CPU time 36.73 seconds
Started May 30 02:32:33 PM PDT 24
Finished May 30 02:33:12 PM PDT 24
Peak memory 198300 kb
Host smart-1b49471d-4f90-4f9c-9949-a7c3aefed0b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822438572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.1822438572
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.519723337
Short name T463
Test name
Test status
Simulation time 344828610858 ps
CPU time 1587.51 seconds
Started May 30 02:32:37 PM PDT 24
Finished May 30 02:59:07 PM PDT 24
Peak memory 198260 kb
Host smart-ad0e0140-bd2b-4808-9998-350be89e37c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=519723337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.519723337
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.3081117393
Short name T235
Test name
Test status
Simulation time 21002538 ps
CPU time 0.61 seconds
Started May 30 02:32:35 PM PDT 24
Finished May 30 02:32:39 PM PDT 24
Peak memory 193908 kb
Host smart-f55f5c9d-a1e5-4814-86ac-642ecee9d146
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081117393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.3081117393
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.1521561330
Short name T469
Test name
Test status
Simulation time 109702166 ps
CPU time 0.87 seconds
Started May 30 02:32:33 PM PDT 24
Finished May 30 02:32:36 PM PDT 24
Peak memory 195384 kb
Host smart-cddc46cc-d103-4b9b-8b0c-c004e410e2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521561330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.1521561330
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.266268276
Short name T321
Test name
Test status
Simulation time 463508106 ps
CPU time 11.91 seconds
Started May 30 02:32:36 PM PDT 24
Finished May 30 02:32:50 PM PDT 24
Peak memory 196732 kb
Host smart-ff7b9fda-c07c-46c5-ab21-68cf53f4af6b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266268276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stres
s.266268276
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.2035344196
Short name T384
Test name
Test status
Simulation time 391238015 ps
CPU time 1.06 seconds
Started May 30 02:32:36 PM PDT 24
Finished May 30 02:32:40 PM PDT 24
Peak memory 197728 kb
Host smart-b64fd3f3-3cf3-46f5-8e07-f359ceb1dca9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035344196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.2035344196
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.3218353129
Short name T346
Test name
Test status
Simulation time 46410696 ps
CPU time 1.42 seconds
Started May 30 02:32:37 PM PDT 24
Finished May 30 02:32:41 PM PDT 24
Peak memory 198084 kb
Host smart-ccd2eb7f-249f-4efc-8e39-507b324eb1c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218353129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.3218353129
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.476110347
Short name T165
Test name
Test status
Simulation time 47288043 ps
CPU time 2.09 seconds
Started May 30 02:32:36 PM PDT 24
Finished May 30 02:32:41 PM PDT 24
Peak memory 198148 kb
Host smart-a301a980-d542-4c29-9437-7a784b54173d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476110347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.gpio_intr_with_filter_rand_intr_event.476110347
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.1779202263
Short name T192
Test name
Test status
Simulation time 237001181 ps
CPU time 1.9 seconds
Started May 30 02:32:32 PM PDT 24
Finished May 30 02:32:36 PM PDT 24
Peak memory 198112 kb
Host smart-f58b260e-50a9-4243-b29c-8631131e7f16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779202263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.1779202263
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.3432047729
Short name T619
Test name
Test status
Simulation time 288269066 ps
CPU time 1.18 seconds
Started May 30 02:32:37 PM PDT 24
Finished May 30 02:32:41 PM PDT 24
Peak memory 196044 kb
Host smart-3fc4a3f2-82e9-46a9-9b32-1699487ce75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432047729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.3432047729
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.3042750168
Short name T119
Test name
Test status
Simulation time 168956004 ps
CPU time 0.97 seconds
Started May 30 02:32:34 PM PDT 24
Finished May 30 02:32:37 PM PDT 24
Peak memory 196068 kb
Host smart-9612d417-f44f-4b8f-aa21-c449c29c107d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042750168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.3042750168
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.3948768814
Short name T340
Test name
Test status
Simulation time 550579459 ps
CPU time 4.66 seconds
Started May 30 02:32:34 PM PDT 24
Finished May 30 02:32:41 PM PDT 24
Peak memory 198028 kb
Host smart-558b1ab4-27f9-4aaa-8c28-7140c767cb62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948768814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.3948768814
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.3616653353
Short name T588
Test name
Test status
Simulation time 29848922 ps
CPU time 0.96 seconds
Started May 30 02:32:32 PM PDT 24
Finished May 30 02:32:35 PM PDT 24
Peak memory 196592 kb
Host smart-be29397d-87b8-499a-880b-fccf2896611f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616653353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.3616653353
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.3957064092
Short name T406
Test name
Test status
Simulation time 80437254 ps
CPU time 1.51 seconds
Started May 30 02:32:35 PM PDT 24
Finished May 30 02:32:39 PM PDT 24
Peak memory 196892 kb
Host smart-33476d6d-8018-4d20-8515-a2bc04f19f44
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957064092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.3957064092
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.1917686760
Short name T488
Test name
Test status
Simulation time 1722564117 ps
CPU time 46.26 seconds
Started May 30 02:32:36 PM PDT 24
Finished May 30 02:33:24 PM PDT 24
Peak memory 198052 kb
Host smart-259bfff1-dbf5-4852-b9db-ef1a64dae770
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917686760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.1917686760
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.3817816318
Short name T38
Test name
Test status
Simulation time 355157094992 ps
CPU time 1995.52 seconds
Started May 30 02:32:37 PM PDT 24
Finished May 30 03:05:56 PM PDT 24
Peak memory 198316 kb
Host smart-17e3a82d-428b-4009-8b52-6d1b9b741e7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3817816318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.3817816318
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.1877388219
Short name T339
Test name
Test status
Simulation time 15224855 ps
CPU time 0.58 seconds
Started May 30 02:32:39 PM PDT 24
Finished May 30 02:32:42 PM PDT 24
Peak memory 194620 kb
Host smart-f69df403-92b4-40ca-8daf-8eacb858e1a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877388219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.1877388219
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.1627662072
Short name T547
Test name
Test status
Simulation time 63286301 ps
CPU time 0.68 seconds
Started May 30 02:32:36 PM PDT 24
Finished May 30 02:32:39 PM PDT 24
Peak memory 194800 kb
Host smart-e8eab478-5727-4f40-b1a8-69942e59a0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627662072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.1627662072
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.2032398424
Short name T500
Test name
Test status
Simulation time 754271328 ps
CPU time 24.1 seconds
Started May 30 02:32:39 PM PDT 24
Finished May 30 02:33:06 PM PDT 24
Peak memory 195544 kb
Host smart-b935f8ee-75be-4914-8e7e-04ec9f752bb6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032398424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.2032398424
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.1195521030
Short name T338
Test name
Test status
Simulation time 78438060 ps
CPU time 0.96 seconds
Started May 30 02:32:38 PM PDT 24
Finished May 30 02:32:42 PM PDT 24
Peak memory 197440 kb
Host smart-80347e53-c8dd-4dd3-b2ac-97d1818a7293
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195521030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.1195521030
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.90074290
Short name T353
Test name
Test status
Simulation time 92392849 ps
CPU time 0.92 seconds
Started May 30 02:32:37 PM PDT 24
Finished May 30 02:32:40 PM PDT 24
Peak memory 195460 kb
Host smart-d48991f5-2539-47a8-a23e-7574c16e8ec4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90074290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.90074290
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.253215928
Short name T118
Test name
Test status
Simulation time 74744665 ps
CPU time 1.49 seconds
Started May 30 02:32:44 PM PDT 24
Finished May 30 02:32:47 PM PDT 24
Peak memory 196980 kb
Host smart-52c45675-5a10-4558-9e3e-e61259aad0ec
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253215928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.gpio_intr_with_filter_rand_intr_event.253215928
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.4155309420
Short name T181
Test name
Test status
Simulation time 150635398 ps
CPU time 3.52 seconds
Started May 30 02:32:35 PM PDT 24
Finished May 30 02:32:41 PM PDT 24
Peak memory 197044 kb
Host smart-7b448059-e7d3-474e-a6f4-67d2510afe97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155309420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.4155309420
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.3169572723
Short name T467
Test name
Test status
Simulation time 41829189 ps
CPU time 1.05 seconds
Started May 30 02:32:37 PM PDT 24
Finished May 30 02:32:40 PM PDT 24
Peak memory 195852 kb
Host smart-2c2d1c6b-1eff-45b2-9e40-160aa10411c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169572723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.3169572723
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.96696661
Short name T178
Test name
Test status
Simulation time 46213921 ps
CPU time 0.65 seconds
Started May 30 02:32:43 PM PDT 24
Finished May 30 02:32:45 PM PDT 24
Peak memory 194344 kb
Host smart-1861b2f2-2699-44be-a965-8873fed12be1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96696661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullup_
pulldown.96696661
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.3058761365
Short name T14
Test name
Test status
Simulation time 605587349 ps
CPU time 4.99 seconds
Started May 30 02:32:36 PM PDT 24
Finished May 30 02:32:43 PM PDT 24
Peak memory 197640 kb
Host smart-550b8bfd-4ca2-4f49-a24a-191b7936671c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058761365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.3058761365
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.2861607809
Short name T133
Test name
Test status
Simulation time 43530105 ps
CPU time 1.04 seconds
Started May 30 02:32:35 PM PDT 24
Finished May 30 02:32:39 PM PDT 24
Peak memory 195808 kb
Host smart-1edaff32-c9bb-4e0e-9879-4c9e61284255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861607809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.2861607809
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2519959542
Short name T144
Test name
Test status
Simulation time 28836533 ps
CPU time 0.82 seconds
Started May 30 02:32:34 PM PDT 24
Finished May 30 02:32:37 PM PDT 24
Peak memory 196036 kb
Host smart-782e02b8-8b76-4466-8213-fa98696f710c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519959542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.2519959542
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.4135254118
Short name T505
Test name
Test status
Simulation time 53732435535 ps
CPU time 207.49 seconds
Started May 30 02:32:41 PM PDT 24
Finished May 30 02:36:10 PM PDT 24
Peak memory 198208 kb
Host smart-4089e232-5f72-4d48-8f00-b7b1ff9ff2a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135254118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.4135254118
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.3918854862
Short name T70
Test name
Test status
Simulation time 40133316620 ps
CPU time 580.04 seconds
Started May 30 02:32:37 PM PDT 24
Finished May 30 02:42:19 PM PDT 24
Peak memory 198208 kb
Host smart-b27b2606-d689-4dc9-8c7c-d5949f2c487f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3918854862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.3918854862
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.1338419987
Short name T656
Test name
Test status
Simulation time 23499511 ps
CPU time 0.63 seconds
Started May 30 02:30:55 PM PDT 24
Finished May 30 02:30:57 PM PDT 24
Peak memory 193976 kb
Host smart-6e02a7df-c5a8-47b4-aef6-444d30b90178
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338419987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.1338419987
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.4027812120
Short name T398
Test name
Test status
Simulation time 34431103 ps
CPU time 0.68 seconds
Started May 30 02:30:59 PM PDT 24
Finished May 30 02:31:01 PM PDT 24
Peak memory 194048 kb
Host smart-0ec84048-1210-4d20-b531-a5d09ac6e34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027812120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.4027812120
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.4057979920
Short name T546
Test name
Test status
Simulation time 328005384 ps
CPU time 10.47 seconds
Started May 30 02:30:56 PM PDT 24
Finished May 30 02:31:08 PM PDT 24
Peak memory 196804 kb
Host smart-ffa9b03e-d4f7-48b4-b462-e4d479623913
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057979920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.4057979920
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.3439176369
Short name T529
Test name
Test status
Simulation time 197510220 ps
CPU time 0.83 seconds
Started May 30 02:30:58 PM PDT 24
Finished May 30 02:30:59 PM PDT 24
Peak memory 196024 kb
Host smart-1341fe8d-4aee-4d2c-9a6f-386f6a0ee2c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439176369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3439176369
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.4264573462
Short name T146
Test name
Test status
Simulation time 17296662 ps
CPU time 0.71 seconds
Started May 30 02:30:59 PM PDT 24
Finished May 30 02:31:01 PM PDT 24
Peak memory 194308 kb
Host smart-9b48cd24-6048-4c6e-a54c-0809d7a9f4a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264573462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.4264573462
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2190267400
Short name T407
Test name
Test status
Simulation time 99256453 ps
CPU time 3.53 seconds
Started May 30 02:30:52 PM PDT 24
Finished May 30 02:30:57 PM PDT 24
Peak memory 198108 kb
Host smart-6ea29132-0ad2-4c84-9575-671f20bb4599
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190267400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.2190267400
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.2355641038
Short name T554
Test name
Test status
Simulation time 124101156 ps
CPU time 3.91 seconds
Started May 30 02:30:56 PM PDT 24
Finished May 30 02:31:01 PM PDT 24
Peak memory 198120 kb
Host smart-642efcb4-3604-4a9a-8aef-07a0bb5aeee4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355641038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
2355641038
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.3928377750
Short name T163
Test name
Test status
Simulation time 99938434 ps
CPU time 1.19 seconds
Started May 30 02:30:59 PM PDT 24
Finished May 30 02:31:02 PM PDT 24
Peak memory 195892 kb
Host smart-d2699aa3-b619-4252-9d80-7bd2c75358c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928377750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.3928377750
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.3765877283
Short name T201
Test name
Test status
Simulation time 212935958 ps
CPU time 1.51 seconds
Started May 30 02:30:53 PM PDT 24
Finished May 30 02:30:56 PM PDT 24
Peak memory 197068 kb
Host smart-ca73f615-a4e7-46dd-b563-c70c555c3dbf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765877283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.3765877283
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.1812931917
Short name T598
Test name
Test status
Simulation time 48664505 ps
CPU time 2.1 seconds
Started May 30 02:30:59 PM PDT 24
Finished May 30 02:31:03 PM PDT 24
Peak memory 198024 kb
Host smart-0d401903-e5fa-4d33-b80f-991dd03875a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812931917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.1812931917
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.1083438646
Short name T449
Test name
Test status
Simulation time 36371099 ps
CPU time 1.17 seconds
Started May 30 02:30:51 PM PDT 24
Finished May 30 02:30:53 PM PDT 24
Peak memory 198028 kb
Host smart-1eef5d1f-d58e-4ef5-b300-17d38e8e4f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083438646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.1083438646
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.1327767742
Short name T326
Test name
Test status
Simulation time 209539471 ps
CPU time 1.04 seconds
Started May 30 02:30:57 PM PDT 24
Finished May 30 02:30:59 PM PDT 24
Peak memory 195628 kb
Host smart-fceb46f4-7122-4e93-98e4-9a4914619916
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327767742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.1327767742
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.1697629568
Short name T624
Test name
Test status
Simulation time 3475403334 ps
CPU time 35.74 seconds
Started May 30 02:30:58 PM PDT 24
Finished May 30 02:31:34 PM PDT 24
Peak memory 198148 kb
Host smart-90e534b9-26a5-4b52-b657-3b4e07cf9e6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697629568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1697629568
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.3385658757
Short name T628
Test name
Test status
Simulation time 103293560276 ps
CPU time 2280.31 seconds
Started May 30 02:30:56 PM PDT 24
Finished May 30 03:08:58 PM PDT 24
Peak memory 198228 kb
Host smart-4e33f01b-e44b-4463-b8f8-de72ed1dc8b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3385658757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.3385658757
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.3730127114
Short name T168
Test name
Test status
Simulation time 42612032 ps
CPU time 0.64 seconds
Started May 30 02:31:16 PM PDT 24
Finished May 30 02:31:19 PM PDT 24
Peak memory 194156 kb
Host smart-db37cee1-06e9-4098-b618-4449521e6e0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730127114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.3730127114
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.4124375741
Short name T495
Test name
Test status
Simulation time 45198629 ps
CPU time 1.01 seconds
Started May 30 02:30:53 PM PDT 24
Finished May 30 02:30:56 PM PDT 24
Peak memory 196688 kb
Host smart-cb8aa47e-d908-470a-b917-475efea93726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124375741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.4124375741
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.438983954
Short name T155
Test name
Test status
Simulation time 219191370 ps
CPU time 11.55 seconds
Started May 30 02:30:54 PM PDT 24
Finished May 30 02:31:07 PM PDT 24
Peak memory 196272 kb
Host smart-841007a0-22ef-444e-9895-7fd9e6373164
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438983954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stress
.438983954
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.206994660
Short name T324
Test name
Test status
Simulation time 46285697 ps
CPU time 0.8 seconds
Started May 30 02:30:52 PM PDT 24
Finished May 30 02:30:55 PM PDT 24
Peak memory 196152 kb
Host smart-9e923962-3d0b-4e01-a9f2-74ab968e42d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206994660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.206994660
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.425856624
Short name T274
Test name
Test status
Simulation time 51085930 ps
CPU time 1.46 seconds
Started May 30 02:31:02 PM PDT 24
Finished May 30 02:31:04 PM PDT 24
Peak memory 198100 kb
Host smart-5c3387d3-0b33-4d79-9cd7-9457f9cfee72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425856624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.425856624
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.3808504110
Short name T242
Test name
Test status
Simulation time 166513356 ps
CPU time 3.54 seconds
Started May 30 02:30:56 PM PDT 24
Finished May 30 02:31:01 PM PDT 24
Peak memory 198172 kb
Host smart-f53af145-5b13-477e-a476-62249ea38fe2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808504110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.3808504110
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.398619828
Short name T334
Test name
Test status
Simulation time 158433134 ps
CPU time 2.49 seconds
Started May 30 02:30:55 PM PDT 24
Finished May 30 02:30:59 PM PDT 24
Peak memory 197064 kb
Host smart-1dec1552-9d4d-4501-a7d7-3fca00830335
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398619828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.398619828
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.155998714
Short name T268
Test name
Test status
Simulation time 110669985 ps
CPU time 1.38 seconds
Started May 30 02:30:57 PM PDT 24
Finished May 30 02:30:59 PM PDT 24
Peak memory 197060 kb
Host smart-3e30f058-dae2-424f-9ab2-90360be6ba70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155998714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.155998714
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.2242799824
Short name T674
Test name
Test status
Simulation time 59241926 ps
CPU time 1.17 seconds
Started May 30 02:30:54 PM PDT 24
Finished May 30 02:30:57 PM PDT 24
Peak memory 196844 kb
Host smart-91a577c4-823a-42b0-adce-73c5bae3a71f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242799824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.2242799824
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.4285890779
Short name T620
Test name
Test status
Simulation time 126158736 ps
CPU time 5.96 seconds
Started May 30 02:30:54 PM PDT 24
Finished May 30 02:31:01 PM PDT 24
Peak memory 198048 kb
Host smart-64c3ce50-3a5e-4d4d-b7f4-6656543ec803
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285890779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.4285890779
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.2020521427
Short name T109
Test name
Test status
Simulation time 1038845081 ps
CPU time 1.33 seconds
Started May 30 02:30:56 PM PDT 24
Finished May 30 02:30:59 PM PDT 24
Peak memory 196456 kb
Host smart-76627ce9-8799-4d6e-aca4-000fc546aed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020521427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.2020521427
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.3248377147
Short name T271
Test name
Test status
Simulation time 35763898 ps
CPU time 1.01 seconds
Started May 30 02:30:56 PM PDT 24
Finished May 30 02:30:58 PM PDT 24
Peak memory 196356 kb
Host smart-ea507907-d412-445f-af1b-689b4ce7fef6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248377147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.3248377147
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.2090874643
Short name T190
Test name
Test status
Simulation time 14126212650 ps
CPU time 85.68 seconds
Started May 30 02:31:13 PM PDT 24
Finished May 30 02:32:40 PM PDT 24
Peak memory 198212 kb
Host smart-e68c8bf1-e1c9-4c84-b90a-0e33a3616815
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090874643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.2090874643
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.3926311916
Short name T37
Test name
Test status
Simulation time 78952063564 ps
CPU time 512.56 seconds
Started May 30 02:31:13 PM PDT 24
Finished May 30 02:39:47 PM PDT 24
Peak memory 198332 kb
Host smart-fac73d3c-d3aa-438e-96d8-8c26dfaf911c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3926311916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.3926311916
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.2912901504
Short name T649
Test name
Test status
Simulation time 41597550 ps
CPU time 0.57 seconds
Started May 30 02:31:15 PM PDT 24
Finished May 30 02:31:18 PM PDT 24
Peak memory 194028 kb
Host smart-17adfa93-0db9-4b87-8697-4c89f08c1e11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912901504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.2912901504
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.293305244
Short name T120
Test name
Test status
Simulation time 87706350 ps
CPU time 0.81 seconds
Started May 30 02:31:10 PM PDT 24
Finished May 30 02:31:11 PM PDT 24
Peak memory 195452 kb
Host smart-4695e495-0fb4-4bc8-9be2-b773c7e6ee57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293305244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.293305244
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.1825422953
Short name T525
Test name
Test status
Simulation time 788265361 ps
CPU time 26.55 seconds
Started May 30 02:31:17 PM PDT 24
Finished May 30 02:31:47 PM PDT 24
Peak memory 195752 kb
Host smart-efcd8d59-2552-441b-920e-2d62ddff6822
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825422953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.1825422953
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.4233883124
Short name T475
Test name
Test status
Simulation time 88474090 ps
CPU time 1.04 seconds
Started May 30 02:31:14 PM PDT 24
Finished May 30 02:31:18 PM PDT 24
Peak memory 197124 kb
Host smart-04856ca2-9929-469e-ae38-e0433ba95bc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233883124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.4233883124
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.605497124
Short name T647
Test name
Test status
Simulation time 200715251 ps
CPU time 1.52 seconds
Started May 30 02:31:12 PM PDT 24
Finished May 30 02:31:15 PM PDT 24
Peak memory 197252 kb
Host smart-b9345be9-abe9-439a-b9c1-a20cd57ec737
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605497124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.605497124
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.3559098701
Short name T256
Test name
Test status
Simulation time 88144756 ps
CPU time 3.41 seconds
Started May 30 02:31:12 PM PDT 24
Finished May 30 02:31:16 PM PDT 24
Peak memory 198100 kb
Host smart-69563c48-21da-466e-bd76-dad5df9dcabb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559098701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.3559098701
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.2946611283
Short name T322
Test name
Test status
Simulation time 278914610 ps
CPU time 2.95 seconds
Started May 30 02:31:11 PM PDT 24
Finished May 30 02:31:15 PM PDT 24
Peak memory 197460 kb
Host smart-4053aa92-3c12-4c91-a669-5f7eaf00f26b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946611283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
2946611283
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.165561933
Short name T502
Test name
Test status
Simulation time 121723443 ps
CPU time 1.51 seconds
Started May 30 02:31:15 PM PDT 24
Finished May 30 02:31:19 PM PDT 24
Peak memory 196620 kb
Host smart-2da79e36-33c3-4ec4-ab10-7b48c9778ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165561933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.165561933
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.1987415373
Short name T417
Test name
Test status
Simulation time 85840637 ps
CPU time 0.78 seconds
Started May 30 02:31:13 PM PDT 24
Finished May 30 02:31:15 PM PDT 24
Peak memory 195656 kb
Host smart-f9960980-c415-4b46-83fa-a17e7ec9c541
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987415373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.1987415373
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.3334132707
Short name T125
Test name
Test status
Simulation time 195684749 ps
CPU time 2.04 seconds
Started May 30 02:31:10 PM PDT 24
Finished May 30 02:31:13 PM PDT 24
Peak memory 197940 kb
Host smart-63ce7348-96f4-4eaa-a00e-61f1474fb9af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334132707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.3334132707
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.3974118037
Short name T609
Test name
Test status
Simulation time 220263085 ps
CPU time 1.2 seconds
Started May 30 02:31:17 PM PDT 24
Finished May 30 02:31:21 PM PDT 24
Peak memory 195896 kb
Host smart-7884e7c2-9090-4730-a61e-bad555881f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974118037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.3974118037
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.2765682108
Short name T623
Test name
Test status
Simulation time 470066200 ps
CPU time 1.53 seconds
Started May 30 02:31:10 PM PDT 24
Finished May 30 02:31:13 PM PDT 24
Peak memory 196756 kb
Host smart-cb640409-5f80-4d3c-b4e2-ec49e84e55b6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765682108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.2765682108
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.1212452036
Short name T197
Test name
Test status
Simulation time 27251390277 ps
CPU time 196.46 seconds
Started May 30 02:31:14 PM PDT 24
Finished May 30 02:34:33 PM PDT 24
Peak memory 198180 kb
Host smart-3f3ad4bc-d797-4f11-93f2-d7a4fb6905e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212452036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.1212452036
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.1363929350
Short name T553
Test name
Test status
Simulation time 97731862750 ps
CPU time 921.49 seconds
Started May 30 02:31:17 PM PDT 24
Finished May 30 02:46:42 PM PDT 24
Peak memory 198272 kb
Host smart-b079b31d-0c57-43b2-92c1-6a7ef0576f2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1363929350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.1363929350
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.3752319484
Short name T528
Test name
Test status
Simulation time 50552130 ps
CPU time 0.6 seconds
Started May 30 02:31:11 PM PDT 24
Finished May 30 02:31:13 PM PDT 24
Peak memory 193952 kb
Host smart-0ab84f0d-efd3-49f2-9154-a0fd4d0b0897
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752319484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.3752319484
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.4047589273
Short name T706
Test name
Test status
Simulation time 128381776 ps
CPU time 0.81 seconds
Started May 30 02:31:14 PM PDT 24
Finished May 30 02:31:17 PM PDT 24
Peak memory 195480 kb
Host smart-7812d080-1f67-45f3-837b-bfa8b3bd6796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047589273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.4047589273
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.1943658527
Short name T355
Test name
Test status
Simulation time 3579740044 ps
CPU time 18.56 seconds
Started May 30 02:31:11 PM PDT 24
Finished May 30 02:31:31 PM PDT 24
Peak memory 196740 kb
Host smart-3c602520-f719-432d-8d70-98c98a11d54d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943658527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.1943658527
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.1012696699
Short name T267
Test name
Test status
Simulation time 590110655 ps
CPU time 0.94 seconds
Started May 30 02:31:12 PM PDT 24
Finished May 30 02:31:15 PM PDT 24
Peak memory 197888 kb
Host smart-ee7ea2d6-f8ac-46d6-9f46-d3a6b59f27b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012696699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.1012696699
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.3972993918
Short name T679
Test name
Test status
Simulation time 155431853 ps
CPU time 0.82 seconds
Started May 30 02:31:10 PM PDT 24
Finished May 30 02:31:12 PM PDT 24
Peak memory 196560 kb
Host smart-84446d39-a210-4afd-bba4-7c38dab4fe1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972993918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.3972993918
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.2980720688
Short name T541
Test name
Test status
Simulation time 473512077 ps
CPU time 1.64 seconds
Started May 30 02:31:11 PM PDT 24
Finished May 30 02:31:14 PM PDT 24
Peak memory 198080 kb
Host smart-6254f609-7d1f-4360-b59c-7913f7215d1b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980720688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.2980720688
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.505562097
Short name T461
Test name
Test status
Simulation time 73864785 ps
CPU time 1.66 seconds
Started May 30 02:31:14 PM PDT 24
Finished May 30 02:31:18 PM PDT 24
Peak memory 196720 kb
Host smart-308a2a11-1fd3-41d1-85df-1178585e202d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505562097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.505562097
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.2147032519
Short name T662
Test name
Test status
Simulation time 112165941 ps
CPU time 0.75 seconds
Started May 30 02:31:14 PM PDT 24
Finished May 30 02:31:16 PM PDT 24
Peak memory 195476 kb
Host smart-153df0f4-da34-48b7-84ab-4fb5e919d11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147032519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.2147032519
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.2040264102
Short name T708
Test name
Test status
Simulation time 64105991 ps
CPU time 1.13 seconds
Started May 30 02:31:10 PM PDT 24
Finished May 30 02:31:12 PM PDT 24
Peak memory 197152 kb
Host smart-8bad55f3-db8b-4de4-adf3-486b94a0112b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040264102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.2040264102
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.1304146973
Short name T566
Test name
Test status
Simulation time 75301266 ps
CPU time 1.5 seconds
Started May 30 02:31:13 PM PDT 24
Finished May 30 02:31:16 PM PDT 24
Peak memory 197976 kb
Host smart-b86f2028-453e-424f-98b2-e2ce7630aa3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304146973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.1304146973
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.2880590471
Short name T350
Test name
Test status
Simulation time 221159117 ps
CPU time 1.26 seconds
Started May 30 02:31:10 PM PDT 24
Finished May 30 02:31:12 PM PDT 24
Peak memory 197980 kb
Host smart-eb1dd161-f1e6-45c5-90ed-f4822da9a595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880590471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.2880590471
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.1160278629
Short name T206
Test name
Test status
Simulation time 313845032 ps
CPU time 1.21 seconds
Started May 30 02:31:15 PM PDT 24
Finished May 30 02:31:19 PM PDT 24
Peak memory 195572 kb
Host smart-ce3d1832-bd1a-418f-9a6d-b35f2a3fbbf0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160278629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.1160278629
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.2192813995
Short name T107
Test name
Test status
Simulation time 12125261604 ps
CPU time 82.67 seconds
Started May 30 02:31:17 PM PDT 24
Finished May 30 02:32:42 PM PDT 24
Peak memory 198272 kb
Host smart-1ec8dc18-dd40-47dd-9dbe-5970832d8e54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192813995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.2192813995
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.3138862983
Short name T490
Test name
Test status
Simulation time 32977189 ps
CPU time 0.6 seconds
Started May 30 02:31:15 PM PDT 24
Finished May 30 02:31:18 PM PDT 24
Peak memory 194084 kb
Host smart-084f2a30-274d-434b-8e1c-909b79687a9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138862983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.3138862983
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.366521994
Short name T232
Test name
Test status
Simulation time 57194604 ps
CPU time 0.79 seconds
Started May 30 02:31:14 PM PDT 24
Finished May 30 02:31:18 PM PDT 24
Peak memory 195404 kb
Host smart-bd40bec4-2504-4886-b40d-f7955c9ea4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366521994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.366521994
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.4116959246
Short name T288
Test name
Test status
Simulation time 686900439 ps
CPU time 10.08 seconds
Started May 30 02:31:16 PM PDT 24
Finished May 30 02:31:29 PM PDT 24
Peak memory 197196 kb
Host smart-0de59498-f4c6-4abb-9e59-78075672955f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116959246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.4116959246
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.571439933
Short name T585
Test name
Test status
Simulation time 87715893 ps
CPU time 0.82 seconds
Started May 30 02:31:15 PM PDT 24
Finished May 30 02:31:18 PM PDT 24
Peak memory 196044 kb
Host smart-a0c46208-6d1e-4e75-9eca-5ace62045b39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571439933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.571439933
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.1152272765
Short name T145
Test name
Test status
Simulation time 114748563 ps
CPU time 0.83 seconds
Started May 30 02:31:11 PM PDT 24
Finished May 30 02:31:13 PM PDT 24
Peak memory 195592 kb
Host smart-473b775d-64b1-491a-a236-4ab0343a11b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152272765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.1152272765
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.2206975208
Short name T174
Test name
Test status
Simulation time 110923933 ps
CPU time 2.61 seconds
Started May 30 02:31:14 PM PDT 24
Finished May 30 02:31:19 PM PDT 24
Peak memory 198040 kb
Host smart-8671e5b9-198d-4b61-8235-1fd857cdeb3c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206975208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.2206975208
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.3178296072
Short name T621
Test name
Test status
Simulation time 437590666 ps
CPU time 2.6 seconds
Started May 30 02:31:13 PM PDT 24
Finished May 30 02:31:17 PM PDT 24
Peak memory 195932 kb
Host smart-942e840a-90bf-4149-96e0-fecd631560f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178296072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
3178296072
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.1492714175
Short name T150
Test name
Test status
Simulation time 25296697 ps
CPU time 1.03 seconds
Started May 30 02:31:11 PM PDT 24
Finished May 30 02:31:13 PM PDT 24
Peak memory 195952 kb
Host smart-3f74106c-2e1c-4002-ade2-59f750bfed67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492714175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.1492714175
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.288569819
Short name T493
Test name
Test status
Simulation time 40049189 ps
CPU time 0.88 seconds
Started May 30 02:31:13 PM PDT 24
Finished May 30 02:31:16 PM PDT 24
Peak memory 195996 kb
Host smart-6327d356-2dba-4848-9e1b-875829cf6b73
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288569819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup_
pulldown.288569819
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.1081962805
Short name T400
Test name
Test status
Simulation time 200099707 ps
CPU time 3.49 seconds
Started May 30 02:31:12 PM PDT 24
Finished May 30 02:31:16 PM PDT 24
Peak memory 198048 kb
Host smart-8f5e38d9-b7f7-4c1d-8db6-b2726da19573
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081962805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.1081962805
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.3806436881
Short name T705
Test name
Test status
Simulation time 869455019 ps
CPU time 1.25 seconds
Started May 30 02:31:13 PM PDT 24
Finished May 30 02:31:16 PM PDT 24
Peak memory 196440 kb
Host smart-2e6d91c6-e89b-4448-bde7-c23d7ef3acca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806436881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.3806436881
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.1360538606
Short name T29
Test name
Test status
Simulation time 90062960 ps
CPU time 0.78 seconds
Started May 30 02:31:13 PM PDT 24
Finished May 30 02:31:15 PM PDT 24
Peak memory 195220 kb
Host smart-c8591802-5959-4ab2-903c-c18d3e791757
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360538606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.1360538606
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.3322520531
Short name T3
Test name
Test status
Simulation time 7146717565 ps
CPU time 90.72 seconds
Started May 30 02:31:11 PM PDT 24
Finished May 30 02:32:43 PM PDT 24
Peak memory 198280 kb
Host smart-1bd1271f-e902-4e6d-8e76-9f4c72bb8450
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322520531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.3322520531
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.572346550
Short name T672
Test name
Test status
Simulation time 27502650949 ps
CPU time 433.74 seconds
Started May 30 02:31:18 PM PDT 24
Finished May 30 02:38:34 PM PDT 24
Peak memory 198276 kb
Host smart-aa4839ff-2b5c-4e59-953b-b2a44b3c1eaa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=572346550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.572346550
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2620376057
Short name T899
Test name
Test status
Simulation time 569109944 ps
CPU time 1.14 seconds
Started May 30 01:15:33 PM PDT 24
Finished May 30 01:15:35 PM PDT 24
Peak memory 196108 kb
Host smart-7eddeaa9-a0d5-4806-85b2-0aac9bac69e4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2620376057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.2620376057
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3209284522
Short name T929
Test name
Test status
Simulation time 71149325 ps
CPU time 0.77 seconds
Started May 30 01:15:33 PM PDT 24
Finished May 30 01:15:35 PM PDT 24
Peak memory 195700 kb
Host smart-f64e2b50-7eb1-476f-afe2-dc46dae504df
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209284522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3209284522
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1459892002
Short name T855
Test name
Test status
Simulation time 43014926 ps
CPU time 0.89 seconds
Started May 30 01:15:30 PM PDT 24
Finished May 30 01:15:32 PM PDT 24
Peak memory 196652 kb
Host smart-2f185f99-7bb1-4a06-9b17-a900a97fb038
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1459892002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.1459892002
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.271817110
Short name T909
Test name
Test status
Simulation time 445329879 ps
CPU time 1.25 seconds
Started May 30 01:15:32 PM PDT 24
Finished May 30 01:15:34 PM PDT 24
Peak memory 198276 kb
Host smart-d27d1e95-4739-4d4e-84fe-63635449a819
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271817110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.271817110
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1086587440
Short name T922
Test name
Test status
Simulation time 36843301 ps
CPU time 0.98 seconds
Started May 30 01:15:47 PM PDT 24
Finished May 30 01:15:49 PM PDT 24
Peak memory 196796 kb
Host smart-45bc21ac-d2fa-4501-b656-b7312bbfc7d4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1086587440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.1086587440
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.780318943
Short name T848
Test name
Test status
Simulation time 47553791 ps
CPU time 0.83 seconds
Started May 30 01:15:47 PM PDT 24
Finished May 30 01:15:49 PM PDT 24
Peak memory 195692 kb
Host smart-2080fdda-03ba-4bcb-9bf5-b50d69a3769e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780318943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.780318943
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3818014120
Short name T858
Test name
Test status
Simulation time 427861522 ps
CPU time 0.95 seconds
Started May 30 01:15:42 PM PDT 24
Finished May 30 01:15:44 PM PDT 24
Peak memory 195836 kb
Host smart-a100207c-5a47-439b-9dae-3212d9cb1d07
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3818014120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.3818014120
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2073535796
Short name T870
Test name
Test status
Simulation time 190298021 ps
CPU time 1.07 seconds
Started May 30 01:15:47 PM PDT 24
Finished May 30 01:15:49 PM PDT 24
Peak memory 196688 kb
Host smart-553fc02a-5f5f-42e5-a504-4fe9c3f1b924
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073535796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2073535796
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.228415401
Short name T938
Test name
Test status
Simulation time 329164021 ps
CPU time 1.44 seconds
Started May 30 01:15:42 PM PDT 24
Finished May 30 01:15:45 PM PDT 24
Peak memory 195896 kb
Host smart-72a46afe-7336-4d28-9926-533dafd9c763
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=228415401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.228415401
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.177591921
Short name T916
Test name
Test status
Simulation time 189461861 ps
CPU time 0.99 seconds
Started May 30 01:15:45 PM PDT 24
Finished May 30 01:15:48 PM PDT 24
Peak memory 198188 kb
Host smart-b8c84854-340e-4035-804d-721510d914d5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177591921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.177591921
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.4079000477
Short name T923
Test name
Test status
Simulation time 138836871 ps
CPU time 1.14 seconds
Started May 30 01:15:46 PM PDT 24
Finished May 30 01:15:48 PM PDT 24
Peak memory 196120 kb
Host smart-82e1e6ae-ba1b-4ed4-9f83-b78456f74b54
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4079000477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.4079000477
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.394599590
Short name T902
Test name
Test status
Simulation time 218482840 ps
CPU time 1.03 seconds
Started May 30 01:15:40 PM PDT 24
Finished May 30 01:15:43 PM PDT 24
Peak memory 196032 kb
Host smart-f1414ee5-0e1f-49ca-977b-0fd2355f18ec
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394599590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.394599590
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1689191736
Short name T888
Test name
Test status
Simulation time 191138960 ps
CPU time 1.36 seconds
Started May 30 01:15:42 PM PDT 24
Finished May 30 01:15:45 PM PDT 24
Peak memory 196780 kb
Host smart-4c8b5fda-b664-4d36-891b-bfdb4d20c69b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1689191736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.1689191736
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1133527173
Short name T864
Test name
Test status
Simulation time 59863585 ps
CPU time 1.03 seconds
Started May 30 01:15:40 PM PDT 24
Finished May 30 01:15:42 PM PDT 24
Peak memory 196120 kb
Host smart-e9232184-3d5f-405d-8dd7-ed4b4cdabd8a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133527173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1133527173
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.127237633
Short name T913
Test name
Test status
Simulation time 56249198 ps
CPU time 1.53 seconds
Started May 30 01:15:43 PM PDT 24
Finished May 30 01:15:46 PM PDT 24
Peak memory 198236 kb
Host smart-d8187266-ed77-4398-b7d3-936c1814878e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=127237633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.127237633
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1157748617
Short name T878
Test name
Test status
Simulation time 43696826 ps
CPU time 1.25 seconds
Started May 30 01:15:41 PM PDT 24
Finished May 30 01:15:44 PM PDT 24
Peak memory 196916 kb
Host smart-2751d4c4-75ce-4d86-9415-567f0e24d15a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157748617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1157748617
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.4273468627
Short name T854
Test name
Test status
Simulation time 32623342 ps
CPU time 1.01 seconds
Started May 30 01:15:40 PM PDT 24
Finished May 30 01:15:42 PM PDT 24
Peak memory 196660 kb
Host smart-a5b2b55c-ac8c-4496-a5a1-3749add37eef
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4273468627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.4273468627
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3935155108
Short name T889
Test name
Test status
Simulation time 82073132 ps
CPU time 1.44 seconds
Started May 30 01:15:45 PM PDT 24
Finished May 30 01:15:48 PM PDT 24
Peak memory 196788 kb
Host smart-c0193bed-1aab-457c-aa8f-9a975288848a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935155108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3935155108
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3736771344
Short name T940
Test name
Test status
Simulation time 286637659 ps
CPU time 1.23 seconds
Started May 30 01:15:41 PM PDT 24
Finished May 30 01:15:43 PM PDT 24
Peak memory 196972 kb
Host smart-49402b8f-5eca-4d50-bacb-7991a5ee25fd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3736771344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.3736771344
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2527861959
Short name T877
Test name
Test status
Simulation time 60499801 ps
CPU time 1.22 seconds
Started May 30 01:15:41 PM PDT 24
Finished May 30 01:15:44 PM PDT 24
Peak memory 196244 kb
Host smart-731f0639-ac44-4383-a42c-e13f5a40bc48
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527861959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2527861959
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2284771821
Short name T939
Test name
Test status
Simulation time 79384972 ps
CPU time 0.96 seconds
Started May 30 01:15:40 PM PDT 24
Finished May 30 01:15:43 PM PDT 24
Peak memory 196588 kb
Host smart-94c3221e-1598-44de-94fc-890de9ab5e4d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2284771821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.2284771821
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3339181944
Short name T925
Test name
Test status
Simulation time 129078352 ps
CPU time 1.14 seconds
Started May 30 01:15:46 PM PDT 24
Finished May 30 01:15:48 PM PDT 24
Peak memory 196872 kb
Host smart-42e10f69-a731-4972-b5c1-6b84d319e0a3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339181944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3339181944
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3539043200
Short name T934
Test name
Test status
Simulation time 41792862 ps
CPU time 1 seconds
Started May 30 01:15:44 PM PDT 24
Finished May 30 01:15:47 PM PDT 24
Peak memory 196824 kb
Host smart-18d38099-72fe-461d-b8b2-3e9bf1487739
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3539043200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.3539043200
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3837706503
Short name T880
Test name
Test status
Simulation time 185391247 ps
CPU time 1.52 seconds
Started May 30 01:15:39 PM PDT 24
Finished May 30 01:15:41 PM PDT 24
Peak memory 197140 kb
Host smart-29b619b5-3b4d-4d9d-bf19-776bc290055e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837706503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3837706503
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.162490839
Short name T897
Test name
Test status
Simulation time 88287403 ps
CPU time 0.78 seconds
Started May 30 01:15:31 PM PDT 24
Finished May 30 01:15:33 PM PDT 24
Peak memory 196484 kb
Host smart-4ad88338-8c7d-489e-b902-2ed28ecfc0b3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=162490839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.162490839
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3774902105
Short name T872
Test name
Test status
Simulation time 100094865 ps
CPU time 1.04 seconds
Started May 30 01:15:31 PM PDT 24
Finished May 30 01:15:33 PM PDT 24
Peak memory 196768 kb
Host smart-e9d907d1-40f3-4712-bcea-a4e57c76837c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774902105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3774902105
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2715727846
Short name T850
Test name
Test status
Simulation time 239863449 ps
CPU time 1.31 seconds
Started May 30 01:15:46 PM PDT 24
Finished May 30 01:15:48 PM PDT 24
Peak memory 196856 kb
Host smart-dbac0f14-9f91-4502-a7e7-c5b161b729bb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2715727846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.2715727846
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1855762752
Short name T873
Test name
Test status
Simulation time 69415722 ps
CPU time 1.26 seconds
Started May 30 01:15:39 PM PDT 24
Finished May 30 01:15:42 PM PDT 24
Peak memory 196912 kb
Host smart-5679a3df-be92-44d1-901a-abd2db82dafd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855762752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1855762752
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2285467682
Short name T883
Test name
Test status
Simulation time 79226660 ps
CPU time 1.49 seconds
Started May 30 01:15:40 PM PDT 24
Finished May 30 01:15:43 PM PDT 24
Peak memory 197160 kb
Host smart-e2c8925f-ad80-491f-aad1-f9130e9f0db3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2285467682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.2285467682
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3710443165
Short name T863
Test name
Test status
Simulation time 35483032 ps
CPU time 0.84 seconds
Started May 30 01:15:47 PM PDT 24
Finished May 30 01:15:49 PM PDT 24
Peak memory 195720 kb
Host smart-0f7dbf7d-04fb-4616-9a88-f5570488afaa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710443165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3710443165
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.698045022
Short name T943
Test name
Test status
Simulation time 36317051 ps
CPU time 0.95 seconds
Started May 30 01:15:39 PM PDT 24
Finished May 30 01:15:41 PM PDT 24
Peak memory 195836 kb
Host smart-af939ba9-4f9a-4e7c-b4f1-10ec0e83ef11
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=698045022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.698045022
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.579178109
Short name T891
Test name
Test status
Simulation time 130411236 ps
CPU time 1.05 seconds
Started May 30 01:15:40 PM PDT 24
Finished May 30 01:15:43 PM PDT 24
Peak memory 196676 kb
Host smart-56a84242-71cd-414d-9303-3d1811f07e15
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579178109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.579178109
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2435450666
Short name T904
Test name
Test status
Simulation time 405556790 ps
CPU time 0.92 seconds
Started May 30 01:15:41 PM PDT 24
Finished May 30 01:15:43 PM PDT 24
Peak memory 196788 kb
Host smart-11aa8afe-2cb3-4847-b0a8-9e78230bd67c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2435450666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.2435450666
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3398480351
Short name T926
Test name
Test status
Simulation time 87690146 ps
CPU time 1.11 seconds
Started May 30 01:15:45 PM PDT 24
Finished May 30 01:15:47 PM PDT 24
Peak memory 196616 kb
Host smart-0c0779fb-109f-4a5d-aa06-a0520984fe14
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398480351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3398480351
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1487797212
Short name T890
Test name
Test status
Simulation time 72726786 ps
CPU time 1.26 seconds
Started May 30 01:15:56 PM PDT 24
Finished May 30 01:15:59 PM PDT 24
Peak memory 196992 kb
Host smart-d138f8b3-2dc0-48cd-bce6-886035f98ec3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1487797212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.1487797212
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3464773226
Short name T892
Test name
Test status
Simulation time 69084912 ps
CPU time 1.42 seconds
Started May 30 01:15:57 PM PDT 24
Finished May 30 01:15:59 PM PDT 24
Peak memory 196972 kb
Host smart-e29c40d7-53ab-430f-b54b-dd351e07681e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464773226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3464773226
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1175271028
Short name T918
Test name
Test status
Simulation time 91578942 ps
CPU time 1.5 seconds
Started May 30 01:15:57 PM PDT 24
Finished May 30 01:15:59 PM PDT 24
Peak memory 198244 kb
Host smart-6415171a-09ce-4210-aa98-7f366a051baf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1175271028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.1175271028
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2420886129
Short name T920
Test name
Test status
Simulation time 57157905 ps
CPU time 1.34 seconds
Started May 30 01:15:54 PM PDT 24
Finished May 30 01:15:56 PM PDT 24
Peak memory 197164 kb
Host smart-bfe4e2f0-0226-4ecf-83ed-e88e9694796a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420886129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2420886129
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3244123084
Short name T847
Test name
Test status
Simulation time 80716751 ps
CPU time 1.37 seconds
Started May 30 01:15:53 PM PDT 24
Finished May 30 01:15:56 PM PDT 24
Peak memory 198148 kb
Host smart-8273b657-5b67-4c97-98e0-b127fcc8aa8a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3244123084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.3244123084
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.540653586
Short name T879
Test name
Test status
Simulation time 293623604 ps
CPU time 0.89 seconds
Started May 30 01:15:55 PM PDT 24
Finished May 30 01:15:57 PM PDT 24
Peak memory 196796 kb
Host smart-ddde1a2a-1780-47e0-b287-e9c518bba215
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540653586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.540653586
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2669445659
Short name T903
Test name
Test status
Simulation time 61353733 ps
CPU time 1.02 seconds
Started May 30 01:15:57 PM PDT 24
Finished May 30 01:15:59 PM PDT 24
Peak memory 196808 kb
Host smart-61a4fad2-07cc-49c6-b020-4f4da7bc1a3c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2669445659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.2669445659
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3499913571
Short name T924
Test name
Test status
Simulation time 310172438 ps
CPU time 1.46 seconds
Started May 30 01:15:58 PM PDT 24
Finished May 30 01:16:00 PM PDT 24
Peak memory 198252 kb
Host smart-a613d513-bce1-4943-a06f-15d32c4bcbf2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499913571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3499913571
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2963007262
Short name T885
Test name
Test status
Simulation time 53651460 ps
CPU time 1.09 seconds
Started May 30 01:15:55 PM PDT 24
Finished May 30 01:15:57 PM PDT 24
Peak memory 195800 kb
Host smart-aaa893b0-d5be-4ef6-bd13-6a751d20b186
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2963007262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.2963007262
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2032773621
Short name T906
Test name
Test status
Simulation time 160918624 ps
CPU time 0.85 seconds
Started May 30 01:15:55 PM PDT 24
Finished May 30 01:15:56 PM PDT 24
Peak memory 195736 kb
Host smart-f271266b-5907-40dc-a9dc-e4de79d66586
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032773621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2032773621
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2186986370
Short name T856
Test name
Test status
Simulation time 82264047 ps
CPU time 1.19 seconds
Started May 30 01:15:55 PM PDT 24
Finished May 30 01:15:57 PM PDT 24
Peak memory 198216 kb
Host smart-be995218-bf3f-43c0-9038-0b2760486e84
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2186986370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.2186986370
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.513019195
Short name T910
Test name
Test status
Simulation time 106746444 ps
CPU time 1.5 seconds
Started May 30 01:15:56 PM PDT 24
Finished May 30 01:15:59 PM PDT 24
Peak memory 196620 kb
Host smart-69b17401-c4cb-49a9-a627-d7136228df0c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513019195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.513019195
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2863102857
Short name T935
Test name
Test status
Simulation time 126506938 ps
CPU time 0.86 seconds
Started May 30 01:15:30 PM PDT 24
Finished May 30 01:15:33 PM PDT 24
Peak memory 196420 kb
Host smart-5b95347d-66c3-4ce8-8bcb-cb4bb0a3f44a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2863102857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.2863102857
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2656385884
Short name T852
Test name
Test status
Simulation time 37127473 ps
CPU time 1.02 seconds
Started May 30 01:15:31 PM PDT 24
Finished May 30 01:15:33 PM PDT 24
Peak memory 198152 kb
Host smart-32e3a16b-6d0a-4929-a982-a272e1f34022
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656385884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2656385884
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1123879243
Short name T896
Test name
Test status
Simulation time 88491586 ps
CPU time 0.92 seconds
Started May 30 01:15:57 PM PDT 24
Finished May 30 01:15:59 PM PDT 24
Peak memory 196316 kb
Host smart-16f0c930-2069-4f9c-8dff-d4545978f8de
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1123879243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.1123879243
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1169604579
Short name T853
Test name
Test status
Simulation time 427385070 ps
CPU time 1.55 seconds
Started May 30 01:15:57 PM PDT 24
Finished May 30 01:15:59 PM PDT 24
Peak memory 197176 kb
Host smart-044c28b5-1f49-4a70-89c7-f47b76163299
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169604579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1169604579
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2429711598
Short name T860
Test name
Test status
Simulation time 361191242 ps
CPU time 1.32 seconds
Started May 30 01:15:56 PM PDT 24
Finished May 30 01:15:59 PM PDT 24
Peak memory 196816 kb
Host smart-529699df-3714-4149-ade0-bba9e0edb42d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2429711598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.2429711598
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1602988621
Short name T944
Test name
Test status
Simulation time 49814511 ps
CPU time 1.12 seconds
Started May 30 01:15:54 PM PDT 24
Finished May 30 01:15:56 PM PDT 24
Peak memory 196684 kb
Host smart-e5859d6b-3cd0-406e-b3df-7d1b8c11092f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602988621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1602988621
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3938709412
Short name T871
Test name
Test status
Simulation time 41435927 ps
CPU time 0.88 seconds
Started May 30 01:15:55 PM PDT 24
Finished May 30 01:15:57 PM PDT 24
Peak memory 196744 kb
Host smart-94c26546-3c2b-4b76-b55e-f523f331a486
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3938709412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.3938709412
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.832589254
Short name T865
Test name
Test status
Simulation time 111863427 ps
CPU time 1.09 seconds
Started May 30 01:15:58 PM PDT 24
Finished May 30 01:16:00 PM PDT 24
Peak memory 196200 kb
Host smart-8b22ac89-b771-49aa-b885-b2c5826bec9a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832589254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.832589254
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2687250926
Short name T859
Test name
Test status
Simulation time 99030191 ps
CPU time 0.91 seconds
Started May 30 01:15:55 PM PDT 24
Finished May 30 01:15:57 PM PDT 24
Peak memory 196912 kb
Host smart-9c8dc9d5-124b-4830-955a-00fb775d4294
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2687250926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.2687250926
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1264174355
Short name T946
Test name
Test status
Simulation time 52460342 ps
CPU time 1.04 seconds
Started May 30 01:15:55 PM PDT 24
Finished May 30 01:15:57 PM PDT 24
Peak memory 198264 kb
Host smart-16dc31d3-dd83-433a-a6c1-a1d45b6d9292
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264174355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1264174355
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2432069947
Short name T874
Test name
Test status
Simulation time 190486354 ps
CPU time 0.93 seconds
Started May 30 01:15:57 PM PDT 24
Finished May 30 01:15:59 PM PDT 24
Peak memory 196908 kb
Host smart-844fc65c-87e1-4b70-bb82-d4cfea32a645
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2432069947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.2432069947
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2105931995
Short name T898
Test name
Test status
Simulation time 101572283 ps
CPU time 0.9 seconds
Started May 30 01:15:57 PM PDT 24
Finished May 30 01:15:59 PM PDT 24
Peak memory 196496 kb
Host smart-06384278-708d-4d82-9c57-013e67e0d4ff
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105931995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2105931995
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3809664578
Short name T932
Test name
Test status
Simulation time 47710144 ps
CPU time 0.99 seconds
Started May 30 01:15:55 PM PDT 24
Finished May 30 01:15:56 PM PDT 24
Peak memory 196672 kb
Host smart-8e8d2f39-f4f8-46fc-aad5-96773b6bbdcf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3809664578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.3809664578
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1775947115
Short name T930
Test name
Test status
Simulation time 90815543 ps
CPU time 1.04 seconds
Started May 30 01:15:55 PM PDT 24
Finished May 30 01:15:57 PM PDT 24
Peak memory 198268 kb
Host smart-a61cca9f-a358-4f7e-8625-3270af8d1d37
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775947115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1775947115
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2952081470
Short name T921
Test name
Test status
Simulation time 43614501 ps
CPU time 1.39 seconds
Started May 30 01:15:54 PM PDT 24
Finished May 30 01:15:56 PM PDT 24
Peak memory 196804 kb
Host smart-25bc0ce3-8f84-4727-a603-1a29004ea762
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2952081470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.2952081470
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1844540070
Short name T919
Test name
Test status
Simulation time 37413395 ps
CPU time 1.08 seconds
Started May 30 01:15:57 PM PDT 24
Finished May 30 01:15:59 PM PDT 24
Peak memory 196192 kb
Host smart-d0a339f6-1352-479f-b6d1-9d1e64ae9909
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844540070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1844540070
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.4124750904
Short name T884
Test name
Test status
Simulation time 37781913 ps
CPU time 1.04 seconds
Started May 30 01:15:56 PM PDT 24
Finished May 30 01:15:58 PM PDT 24
Peak memory 196832 kb
Host smart-e33324e4-24db-424b-a35a-b431463a8ee9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4124750904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.4124750904
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2168463136
Short name T851
Test name
Test status
Simulation time 270338928 ps
CPU time 1.32 seconds
Started May 30 01:16:05 PM PDT 24
Finished May 30 01:16:08 PM PDT 24
Peak memory 196832 kb
Host smart-e88320a3-2cf2-4f0f-8db2-2bd041505a94
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168463136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2168463136
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1991790210
Short name T886
Test name
Test status
Simulation time 265175174 ps
CPU time 1.36 seconds
Started May 30 01:16:08 PM PDT 24
Finished May 30 01:16:11 PM PDT 24
Peak memory 196712 kb
Host smart-7efbea4f-ff71-4200-964d-5779dcda6498
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1991790210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.1991790210
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3057806057
Short name T849
Test name
Test status
Simulation time 330045323 ps
CPU time 1.4 seconds
Started May 30 01:16:06 PM PDT 24
Finished May 30 01:16:10 PM PDT 24
Peak memory 195868 kb
Host smart-f4ac2c2b-80b5-4aec-a2ca-b302be8a21b9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057806057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3057806057
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3070983665
Short name T917
Test name
Test status
Simulation time 40620457 ps
CPU time 1.07 seconds
Started May 30 01:16:04 PM PDT 24
Finished May 30 01:16:07 PM PDT 24
Peak memory 196100 kb
Host smart-ab3b07b5-ee2d-4e50-b92a-da63669c24a2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3070983665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.3070983665
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.795935182
Short name T936
Test name
Test status
Simulation time 76302262 ps
CPU time 1.33 seconds
Started May 30 01:16:07 PM PDT 24
Finished May 30 01:16:10 PM PDT 24
Peak memory 197512 kb
Host smart-29f709e9-87ba-424c-b29e-75d495619bc4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795935182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.795935182
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.77570646
Short name T937
Test name
Test status
Simulation time 99030702 ps
CPU time 1.62 seconds
Started May 30 01:15:31 PM PDT 24
Finished May 30 01:15:34 PM PDT 24
Peak memory 197032 kb
Host smart-2dc3d9c1-b326-4d76-9922-636265676482
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=77570646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.77570646
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3162362583
Short name T861
Test name
Test status
Simulation time 888182161 ps
CPU time 1.23 seconds
Started May 30 01:15:32 PM PDT 24
Finished May 30 01:15:35 PM PDT 24
Peak memory 198280 kb
Host smart-a0370868-1a54-470d-b4cb-a9f2a7655ea2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162362583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3162362583
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1684179038
Short name T868
Test name
Test status
Simulation time 986511103 ps
CPU time 1.14 seconds
Started May 30 01:16:07 PM PDT 24
Finished May 30 01:16:10 PM PDT 24
Peak memory 196768 kb
Host smart-2929b770-58ad-41d4-a676-bb74b2722f42
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1684179038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.1684179038
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3126343706
Short name T875
Test name
Test status
Simulation time 271573483 ps
CPU time 1.14 seconds
Started May 30 01:16:08 PM PDT 24
Finished May 30 01:16:11 PM PDT 24
Peak memory 196912 kb
Host smart-9ad412f7-a458-4e42-9cdb-f0b94db6242f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126343706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3126343706
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.492627625
Short name T927
Test name
Test status
Simulation time 803064149 ps
CPU time 1.39 seconds
Started May 30 01:16:06 PM PDT 24
Finished May 30 01:16:10 PM PDT 24
Peak memory 196840 kb
Host smart-863bad3f-a3e8-48a4-b60c-0cf96b44de9f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=492627625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.492627625
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2415015675
Short name T862
Test name
Test status
Simulation time 51791407 ps
CPU time 1.11 seconds
Started May 30 01:16:10 PM PDT 24
Finished May 30 01:16:12 PM PDT 24
Peak memory 198212 kb
Host smart-aa035d82-74a4-46f2-a0f0-77da5d59cbda
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415015675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2415015675
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1443890055
Short name T893
Test name
Test status
Simulation time 44648933 ps
CPU time 1.27 seconds
Started May 30 01:16:09 PM PDT 24
Finished May 30 01:16:12 PM PDT 24
Peak memory 196180 kb
Host smart-b6d27004-070f-4264-bdfb-9b69080ac3fc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1443890055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1443890055
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2595272779
Short name T942
Test name
Test status
Simulation time 89255542 ps
CPU time 0.88 seconds
Started May 30 01:16:10 PM PDT 24
Finished May 30 01:16:12 PM PDT 24
Peak memory 196992 kb
Host smart-4f9ac3ac-3400-4680-ad2f-b2b38cf9ff52
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595272779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2595272779
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3282184502
Short name T941
Test name
Test status
Simulation time 71876184 ps
CPU time 1.35 seconds
Started May 30 01:16:09 PM PDT 24
Finished May 30 01:16:12 PM PDT 24
Peak memory 197108 kb
Host smart-aafb03a3-8df8-4580-b945-c847b20c3c34
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3282184502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.3282184502
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1147342489
Short name T876
Test name
Test status
Simulation time 241880731 ps
CPU time 1.36 seconds
Started May 30 01:16:06 PM PDT 24
Finished May 30 01:16:09 PM PDT 24
Peak memory 197196 kb
Host smart-6b757aa5-ed2e-4f3b-a317-0bdb0e11a5aa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147342489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1147342489
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2496146493
Short name T895
Test name
Test status
Simulation time 434511664 ps
CPU time 1.08 seconds
Started May 30 01:16:05 PM PDT 24
Finished May 30 01:16:07 PM PDT 24
Peak memory 196764 kb
Host smart-33103926-80bb-4771-af63-0339ed2f9643
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2496146493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.2496146493
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4107668652
Short name T905
Test name
Test status
Simulation time 125209109 ps
CPU time 1.26 seconds
Started May 30 01:16:08 PM PDT 24
Finished May 30 01:16:11 PM PDT 24
Peak memory 198276 kb
Host smart-9a526099-6031-4782-8b41-f8a902922b5b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107668652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4107668652
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2095552191
Short name T866
Test name
Test status
Simulation time 176905618 ps
CPU time 0.94 seconds
Started May 30 01:16:04 PM PDT 24
Finished May 30 01:16:05 PM PDT 24
Peak memory 195872 kb
Host smart-f2f73d45-3e9d-463f-b0ab-4cff2759d155
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2095552191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.2095552191
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1122449495
Short name T894
Test name
Test status
Simulation time 113343801 ps
CPU time 1.13 seconds
Started May 30 01:16:07 PM PDT 24
Finished May 30 01:16:10 PM PDT 24
Peak memory 196844 kb
Host smart-4413ce7f-1edc-41f4-8cff-7238a27fe5da
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122449495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1122449495
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2799491686
Short name T882
Test name
Test status
Simulation time 220809024 ps
CPU time 1.32 seconds
Started May 30 01:16:06 PM PDT 24
Finished May 30 01:16:09 PM PDT 24
Peak memory 198212 kb
Host smart-2a5624b0-02f8-4544-8782-ae73551a03ca
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2799491686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.2799491686
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3657687583
Short name T907
Test name
Test status
Simulation time 243762601 ps
CPU time 0.88 seconds
Started May 30 01:16:05 PM PDT 24
Finished May 30 01:16:07 PM PDT 24
Peak memory 196708 kb
Host smart-bcc7e458-5807-4d99-9556-81df0bd3edf8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657687583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3657687583
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3879446809
Short name T908
Test name
Test status
Simulation time 50652022 ps
CPU time 0.92 seconds
Started May 30 01:16:06 PM PDT 24
Finished May 30 01:16:09 PM PDT 24
Peak memory 195796 kb
Host smart-67ebb8e0-c928-4514-9a4f-ba090b6f2546
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3879446809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.3879446809
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1495306136
Short name T869
Test name
Test status
Simulation time 265789313 ps
CPU time 0.98 seconds
Started May 30 01:16:04 PM PDT 24
Finished May 30 01:16:06 PM PDT 24
Peak memory 196812 kb
Host smart-16e983cc-9fae-4ce4-8903-b8fd8751e8e4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495306136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1495306136
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3410622450
Short name T867
Test name
Test status
Simulation time 31795573 ps
CPU time 0.91 seconds
Started May 30 01:16:06 PM PDT 24
Finished May 30 01:16:08 PM PDT 24
Peak memory 195576 kb
Host smart-fd630a69-8b0d-48e1-8042-6268f1374ff7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3410622450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3410622450
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2731129939
Short name T911
Test name
Test status
Simulation time 194450329 ps
CPU time 1.1 seconds
Started May 30 01:16:05 PM PDT 24
Finished May 30 01:16:08 PM PDT 24
Peak memory 196824 kb
Host smart-6814879d-0b8b-4039-9a52-c42e629ca069
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731129939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2731129939
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1260285016
Short name T901
Test name
Test status
Simulation time 58597373 ps
CPU time 0.8 seconds
Started May 30 01:16:04 PM PDT 24
Finished May 30 01:16:06 PM PDT 24
Peak memory 195744 kb
Host smart-38479e6b-3a48-47aa-a774-68e5b00e4cd1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1260285016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.1260285016
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3080620030
Short name T857
Test name
Test status
Simulation time 66582628 ps
CPU time 0.8 seconds
Started May 30 01:16:10 PM PDT 24
Finished May 30 01:16:12 PM PDT 24
Peak memory 195552 kb
Host smart-9eebf7bd-8961-430a-a363-45075b198678
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080620030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3080620030
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1141848566
Short name T928
Test name
Test status
Simulation time 30432848 ps
CPU time 0.99 seconds
Started May 30 01:15:28 PM PDT 24
Finished May 30 01:15:30 PM PDT 24
Peak memory 196808 kb
Host smart-79045cd6-a53c-47cb-a9db-e21941da6b90
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1141848566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.1141848566
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1702763172
Short name T912
Test name
Test status
Simulation time 172947147 ps
CPU time 1.39 seconds
Started May 30 01:15:29 PM PDT 24
Finished May 30 01:15:32 PM PDT 24
Peak memory 197092 kb
Host smart-5baece64-97cd-4082-a09e-c63f54996346
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702763172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1702763172
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1238608016
Short name T945
Test name
Test status
Simulation time 53797021 ps
CPU time 1.41 seconds
Started May 30 01:15:30 PM PDT 24
Finished May 30 01:15:33 PM PDT 24
Peak memory 196856 kb
Host smart-5c92956e-1e52-4066-ae80-3a316c413428
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1238608016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.1238608016
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.996733137
Short name T900
Test name
Test status
Simulation time 74681556 ps
CPU time 1.43 seconds
Started May 30 01:15:30 PM PDT 24
Finished May 30 01:15:33 PM PDT 24
Peak memory 195856 kb
Host smart-1019b4f2-3060-4ef0-a63c-06b3ae48da81
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996733137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.996733137
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.983441509
Short name T887
Test name
Test status
Simulation time 918433115 ps
CPU time 1.09 seconds
Started May 30 01:15:47 PM PDT 24
Finished May 30 01:15:49 PM PDT 24
Peak memory 196768 kb
Host smart-43cbe34d-b02a-4ddf-82f9-a25d28bdc2f2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=983441509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.983441509
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1193689638
Short name T931
Test name
Test status
Simulation time 53426591 ps
CPU time 1.07 seconds
Started May 30 01:15:40 PM PDT 24
Finished May 30 01:15:43 PM PDT 24
Peak memory 196168 kb
Host smart-c1df5a7e-9407-416c-a17d-bf84c21a527a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193689638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1193689638
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3698474996
Short name T914
Test name
Test status
Simulation time 46989185 ps
CPU time 0.98 seconds
Started May 30 01:15:45 PM PDT 24
Finished May 30 01:15:48 PM PDT 24
Peak memory 196656 kb
Host smart-1eb44232-e972-45a2-b360-244a67831e54
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3698474996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.3698474996
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2044751194
Short name T915
Test name
Test status
Simulation time 155587811 ps
CPU time 1.24 seconds
Started May 30 01:15:40 PM PDT 24
Finished May 30 01:15:43 PM PDT 24
Peak memory 197012 kb
Host smart-e047d765-99a5-4b82-93e1-cbeece8808f3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044751194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2044751194
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1057301802
Short name T933
Test name
Test status
Simulation time 109944172 ps
CPU time 1.17 seconds
Started May 30 01:15:46 PM PDT 24
Finished May 30 01:15:48 PM PDT 24
Peak memory 196032 kb
Host smart-3f142294-c385-40e9-8297-738f6626b584
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1057301802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.1057301802
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2280640234
Short name T881
Test name
Test status
Simulation time 64871613 ps
CPU time 1.19 seconds
Started May 30 01:15:40 PM PDT 24
Finished May 30 01:15:42 PM PDT 24
Peak memory 197804 kb
Host smart-3164db38-20a6-4290-b6ae-76d90f816877
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280640234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2280640234
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%