Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4443544	1			T22	1		T1	8199		T11	13228
all_pins[1]	4443544	1			T22	1		T1	8199		T11	13228
all_pins[2]	4443544	1			T22	1		T1	8199		T11	13228
all_pins[3]	4443544	1			T22	1		T1	8199		T11	13228
all_pins[4]	4443544	1			T22	1		T1	8199		T11	13228
all_pins[5]	4443544	1			T22	1		T1	8199		T11	13228
all_pins[6]	4443544	1			T22	1		T1	8199		T11	13228
all_pins[7]	4443544	1			T22	1		T1	8199		T11	13228
all_pins[8]	4443544	1			T22	1		T1	8199		T11	13228
all_pins[9]	4443544	1			T22	1		T1	8199		T11	13228
all_pins[10]	4443544	1			T22	1		T1	8199		T11	13228
all_pins[11]	4443544	1			T22	1		T1	8199		T11	13228
all_pins[12]	4443544	1			T22	1		T1	8199		T11	13228
all_pins[13]	4443544	1			T22	1		T1	8199		T11	13228
all_pins[14]	4443544	1			T22	1		T1	8199		T11	13228
all_pins[15]	4443544	1			T22	1		T1	8199		T11	13228
all_pins[16]	4443544	1			T22	1		T1	8199		T11	13228
all_pins[17]	4443544	1			T22	1		T1	8199		T11	13228
all_pins[18]	4443544	1			T22	1		T1	8199		T11	13228
all_pins[19]	4443544	1			T22	1		T1	8199		T11	13228
all_pins[20]	4443544	1			T22	1		T1	8199		T11	13228
all_pins[21]	4443544	1			T22	1		T1	8199		T11	13228
all_pins[22]	4443544	1			T22	1		T1	8199		T11	13228
all_pins[23]	4443544	1			T22	1		T1	8199		T11	13228
all_pins[24]	4443544	1			T22	1		T1	8199		T11	13228
all_pins[25]	4443544	1			T22	1		T1	8199		T11	13228
all_pins[26]	4443544	1			T22	1		T1	8199		T11	13228
all_pins[27]	4443544	1			T22	1		T1	8199		T11	13228
all_pins[28]	4443544	1			T22	1		T1	8199		T11	13228
all_pins[29]	4443544	1			T22	1		T1	8199		T11	13228
all_pins[30]	4443544	1			T22	1		T1	8199		T11	13228
all_pins[31]	4443544	1			T22	1		T1	8199		T11	13228

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	88313630	1			T22	32		T1	162423		T11	262344
values[0x1]	53879778	1			T1	99945		T11	160952		T13	1375
transitions[0x0=>0x1]	32297280	1			T1	59542		T11	95523		T13	828
transitions[0x1=>0x0]	32297124	1			T1	59541		T11	95523		T13	828

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2752465	1			T22	1		T1	5123		T11	7920
all_pins[0]	values[0x1]	1691079	1			T1	3076		T11	5308		T13	46
all_pins[0]	transitions[0x0=>0x1]	1047687	1			T1	1926		T11	3203		T13	35
all_pins[0]	transitions[0x1=>0x0]	1039616	1			T1	2050		T11	2995		T13	31
all_pins[1]	values[0x0]	2758354	1			T22	1		T1	4959		T11	7992
all_pins[1]	values[0x1]	1685190	1			T1	3240		T11	5236		T13	33
all_pins[1]	transitions[0x0=>0x1]	1007866	1			T1	1920		T11	3110		T13	14
all_pins[1]	transitions[0x1=>0x0]	1013755	1			T1	1756		T11	3182		T13	27
all_pins[2]	values[0x0]	2760435	1			T22	1		T1	5243		T11	8617
all_pins[2]	values[0x1]	1683109	1			T1	2956		T11	4611		T13	31
all_pins[2]	transitions[0x0=>0x1]	1007741	1			T1	1711		T11	2682		T13	17
all_pins[2]	transitions[0x1=>0x0]	1009822	1			T1	1995		T11	3307		T13	19
all_pins[3]	values[0x0]	2759772	1			T22	1		T1	4959		T11	8072
all_pins[3]	values[0x1]	1683772	1			T1	3240		T11	5156		T13	39
all_pins[3]	transitions[0x0=>0x1]	1009290	1			T1	2011		T11	3297		T13	33
all_pins[3]	transitions[0x1=>0x0]	1008627	1			T1	1727		T11	2752		T13	25
all_pins[4]	values[0x0]	2760124	1			T22	1		T1	5020		T11	8398
all_pins[4]	values[0x1]	1683420	1			T1	3179		T11	4830		T13	53
all_pins[4]	transitions[0x0=>0x1]	1008321	1			T1	1819		T11	2772		T13	32
all_pins[4]	transitions[0x1=>0x0]	1008673	1			T1	1880		T11	3098		T13	18
all_pins[5]	values[0x0]	2761258	1			T22	1		T1	5039		T11	8147
all_pins[5]	values[0x1]	1682286	1			T1	3160		T11	5081		T13	26
all_pins[5]	transitions[0x0=>0x1]	1006699	1			T1	1931		T11	3045		T13	13
all_pins[5]	transitions[0x1=>0x0]	1007833	1			T1	1950		T11	2794		T13	40
all_pins[6]	values[0x0]	2758915	1			T22	1		T1	5099		T11	8236
all_pins[6]	values[0x1]	1684629	1			T1	3100		T11	4992		T13	31
all_pins[6]	transitions[0x0=>0x1]	1008993	1			T1	1810		T11	2881		T13	24
all_pins[6]	transitions[0x1=>0x0]	1006650	1			T1	1870		T11	2970		T13	19
all_pins[7]	values[0x0]	2759374	1			T22	1		T1	4949		T11	8133
all_pins[7]	values[0x1]	1684170	1			T1	3250		T11	5095		T13	41
all_pins[7]	transitions[0x0=>0x1]	1008075	1			T1	1944		T11	3013		T13	32
all_pins[7]	transitions[0x1=>0x0]	1008534	1			T1	1794		T11	2910		T13	22
all_pins[8]	values[0x0]	2761023	1			T22	1		T1	5012		T11	8271
all_pins[8]	values[0x1]	1682521	1			T1	3187		T11	4957		T13	37
all_pins[8]	transitions[0x0=>0x1]	1005033	1			T1	1835		T11	2999		T13	19
all_pins[8]	transitions[0x1=>0x0]	1006682	1			T1	1898		T11	3137		T13	23
all_pins[9]	values[0x0]	2763932	1			T22	1		T1	5189		T11	8189
all_pins[9]	values[0x1]	1679612	1			T1	3010		T11	5039		T13	33
all_pins[9]	transitions[0x0=>0x1]	1007420	1			T1	1812		T11	3038		T13	23
all_pins[9]	transitions[0x1=>0x0]	1010329	1			T1	1989		T11	2956		T13	27
all_pins[10]	values[0x0]	2759682	1			T22	1		T1	5103		T11	7978
all_pins[10]	values[0x1]	1683862	1			T1	3096		T11	5250		T13	66
all_pins[10]	transitions[0x0=>0x1]	1009829	1			T1	1899		T11	3066		T13	48
all_pins[10]	transitions[0x1=>0x0]	1005579	1			T1	1813		T11	2855		T13	15
all_pins[11]	values[0x0]	2756272	1			T22	1		T1	5268		T11	8226
all_pins[11]	values[0x1]	1687272	1			T1	2931		T11	5002		T13	50
all_pins[11]	transitions[0x0=>0x1]	1009362	1			T1	1649		T11	2988		T13	22
all_pins[11]	transitions[0x1=>0x0]	1005952	1			T1	1814		T11	3236		T13	38
all_pins[12]	values[0x0]	2758587	1			T22	1		T1	5117		T11	8469
all_pins[12]	values[0x1]	1684957	1			T1	3082		T11	4759		T13	63
all_pins[12]	transitions[0x0=>0x1]	1007732	1			T1	1882		T11	2921		T13	32
all_pins[12]	transitions[0x1=>0x0]	1010047	1			T1	1731		T11	3164		T13	19
all_pins[13]	values[0x0]	2757584	1			T22	1		T1	5181		T11	8267
all_pins[13]	values[0x1]	1685960	1			T1	3018		T11	4961		T13	52
all_pins[13]	transitions[0x0=>0x1]	1008338	1			T1	1847		T11	2974		T13	19
all_pins[13]	transitions[0x1=>0x0]	1007335	1			T1	1911		T11	2772		T13	30
all_pins[14]	values[0x0]	2756841	1			T22	1		T1	5199		T11	8170
all_pins[14]	values[0x1]	1686703	1			T1	3000		T11	5058		T13	28
all_pins[14]	transitions[0x0=>0x1]	1008125	1			T1	1925		T11	3026		T13	16
all_pins[14]	transitions[0x1=>0x0]	1007382	1			T1	1943		T11	2929		T13	40
all_pins[15]	values[0x0]	2753177	1			T22	1		T1	4838		T11	8544
all_pins[15]	values[0x1]	1690367	1			T1	3361		T11	4684		T13	35
all_pins[15]	transitions[0x0=>0x1]	1012793	1			T1	2107		T11	2712		T13	24
all_pins[15]	transitions[0x1=>0x0]	1009129	1			T1	1746		T11	3086		T13	17
all_pins[16]	values[0x0]	2759407	1			T22	1		T1	4971		T11	8247
all_pins[16]	values[0x1]	1684137	1			T1	3228		T11	4981		T13	31
all_pins[16]	transitions[0x0=>0x1]	1003603	1			T1	1805		T11	3038		T13	19
all_pins[16]	transitions[0x1=>0x0]	1009833	1			T1	1938		T11	2741		T13	23
all_pins[17]	values[0x0]	2758124	1			T22	1		T1	5288		T11	8095
all_pins[17]	values[0x1]	1685420	1			T1	2911		T11	5133		T13	44
all_pins[17]	transitions[0x0=>0x1]	1006802	1			T1	1697		T11	3062		T13	43
all_pins[17]	transitions[0x1=>0x0]	1005519	1			T1	2014		T11	2910		T13	30
all_pins[18]	values[0x0]	2767275	1			T22	1		T1	5217		T11	8223
all_pins[18]	values[0x1]	1676269	1			T1	2982		T11	5005		T13	67
all_pins[18]	transitions[0x0=>0x1]	1001663	1			T1	1886		T11	2903		T13	30
all_pins[18]	transitions[0x1=>0x0]	1010814	1			T1	1815		T11	3031		T13	7
all_pins[19]	values[0x0]	2763173	1			T22	1		T1	5089		T11	8167
all_pins[19]	values[0x1]	1680371	1			T1	3110		T11	5061		T13	24
all_pins[19]	transitions[0x0=>0x1]	1007563	1			T1	1908		T11	2970		T13	10
all_pins[19]	transitions[0x1=>0x0]	1003461	1			T1	1780		T11	2914		T13	53
all_pins[20]	values[0x0]	2759156	1			T22	1		T1	5035		T11	8313
all_pins[20]	values[0x1]	1684388	1			T1	3164		T11	4915		T13	54
all_pins[20]	transitions[0x0=>0x1]	1009491	1			T1	1877		T11	2874		T13	40
all_pins[20]	transitions[0x1=>0x0]	1005474	1			T1	1823		T11	3020		T13	10
all_pins[21]	values[0x0]	2756450	1			T22	1		T1	5283		T11	8037
all_pins[21]	values[0x1]	1687094	1			T1	2916		T11	5191		T13	43
all_pins[21]	transitions[0x0=>0x1]	1013699	1			T1	1698		T11	3222		T13	20
all_pins[21]	transitions[0x1=>0x0]	1010993	1			T1	1946		T11	2946		T13	31
all_pins[22]	values[0x0]	2763375	1			T22	1		T1	5000		T11	8284
all_pins[22]	values[0x1]	1680169	1			T1	3199		T11	4944		T13	48
all_pins[22]	transitions[0x0=>0x1]	1005759	1			T1	1969		T11	2708		T13	23
all_pins[22]	transitions[0x1=>0x0]	1012684	1			T1	1686		T11	2955		T13	18
all_pins[23]	values[0x0]	2760455	1			T22	1		T1	5019		T11	8264
all_pins[23]	values[0x1]	1683089	1			T1	3180		T11	4964		T13	54
all_pins[23]	transitions[0x0=>0x1]	1009361	1			T1	1870		T11	2916		T13	34
all_pins[23]	transitions[0x1=>0x0]	1006441	1			T1	1889		T11	2896		T13	28
all_pins[24]	values[0x0]	2756259	1			T22	1		T1	5145		T11	7853
all_pins[24]	values[0x1]	1687285	1			T1	3054		T11	5375		T13	50
all_pins[24]	transitions[0x0=>0x1]	1012234	1			T1	1750		T11	3291		T13	27
all_pins[24]	transitions[0x1=>0x0]	1008038	1			T1	1876		T11	2880		T13	31
all_pins[25]	values[0x0]	2758469	1			T22	1		T1	5098		T11	8153
all_pins[25]	values[0x1]	1685075	1			T1	3101		T11	5075		T13	60
all_pins[25]	transitions[0x0=>0x1]	1005897	1			T1	1921		T11	2912		T13	33
all_pins[25]	transitions[0x1=>0x0]	1008107	1			T1	1874		T11	3212		T13	23
all_pins[26]	values[0x0]	2758502	1			T22	1		T1	4947		T11	8220
all_pins[26]	values[0x1]	1685042	1			T1	3252		T11	5008		T13	43
all_pins[26]	transitions[0x0=>0x1]	1008026	1			T1	1879		T11	3029		T13	19
all_pins[26]	transitions[0x1=>0x0]	1008059	1			T1	1728		T11	3096		T13	36
all_pins[27]	values[0x0]	2764581	1			T22	1		T1	4957		T11	8388
all_pins[27]	values[0x1]	1678963	1			T1	3242		T11	4840		T13	48
all_pins[27]	transitions[0x0=>0x1]	1004777	1			T1	1830		T11	2660		T13	33
all_pins[27]	transitions[0x1=>0x0]	1010856	1			T1	1840		T11	2828		T13	28
all_pins[28]	values[0x0]	2762153	1			T22	1		T1	4836		T11	8208
all_pins[28]	values[0x1]	1681391	1			T1	3363		T11	5020		T13	29
all_pins[28]	transitions[0x0=>0x1]	1008115	1			T1	1955		T11	3063		T13	15
all_pins[28]	transitions[0x1=>0x0]	1005687	1			T1	1834		T11	2883		T13	34
all_pins[29]	values[0x0]	2765271	1			T22	1		T1	5187		T11	8054
all_pins[29]	values[0x1]	1678273	1			T1	3012		T11	5174		T13	46
all_pins[29]	transitions[0x0=>0x1]	1007187	1			T1	1652		T11	3120		T13	36
all_pins[29]	transitions[0x1=>0x0]	1010305	1			T1	2003		T11	2966		T13	19
all_pins[30]	values[0x0]	2762805	1			T22	1		T1	5055		T11	8081
all_pins[30]	values[0x1]	1680739	1			T1	3144		T11	5147		T13	28
all_pins[30]	transitions[0x0=>0x1]	1008553	1			T1	1884		T11	2978		T13	15
all_pins[30]	transitions[0x1=>0x0]	1006087	1			T1	1752		T11	3005		T13	33
all_pins[31]	values[0x0]	2760380	1			T22	1		T1	4998		T11	8128
all_pins[31]	values[0x1]	1683164	1			T1	3201		T11	5100		T13	42
all_pins[31]	transitions[0x0=>0x1]	1011246	1			T1	1933		T11	3050		T13	28
all_pins[31]	transitions[0x1=>0x0]	1008821	1			T1	1876		T11	3097		T13	14