Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[1]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[2]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[3]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[4]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[5]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[6]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[7]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[8]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[9]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[10]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[11]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[12]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[13]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[14]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[15]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[16]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[17]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[18]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[19]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[20]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[21]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[22]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[23]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[24]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[25]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[26]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[27]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[28]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[29]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[30]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[31]	14462017	1			T22	667		T1	25633		T11	40531

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

279243073

1

T22

4270

T1

268014

T11

448080

auto[1]

183541471

1

T22

17074

T1

552242

T11

848912

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

370923674

1

T22

15951

T1

603600

T11

100694

auto[1]

91860870

1

T22

5393

T1

216656

T11

290047

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

343966868

1

T22

10722

T1

554184

T11

928555

auto[1]

118817676

1

T22

10622

T1

266072

T11

368437

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5407652	1			T22	30		T1	4556		T11	8946
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3900573	1			T22	212		T1	9336		T11	15382
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1442824	1			T22	106		T1	3423		T11	4632
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1870013	1			T22	27		T1	274		T11	464
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	410505	1			T22	200		T1	4467		T11	6699
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1430450	1			T22	92		T1	3577		T11	4408
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5414155	1			T22	29		T1	4702		T11	8971
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3895005	1			T22	239		T1	9300		T11	15730
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1442585	1			T22	77		T1	3305		T11	4881
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1870360	1			T22	22		T1	308		T11	448
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	410005	1			T22	230		T1	4781		T11	6232
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1429907	1			T22	70		T1	3237		T11	4269
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5405894	1			T22	24		T1	4655		T11	8994
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3894055	1			T22	219		T1	9079		T11	15190
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1442090	1			T22	121		T1	3607		T11	4491
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1877656	1			T22	24		T1	249		T11	493
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	409623	1			T22	162		T1	4856		T11	6944
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1432699	1			T22	117		T1	3187		T11	4419
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5405477	1			T22	20		T1	4597		T11	8938
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3901008	1			T22	239		T1	9040		T11	15241
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1444513	1			T22	62		T1	3274		T11	4270
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1873472	1			T22	31		T1	318		T11	498
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	408130	1			T22	251		T1	5246		T11	6863
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1429417	1			T22	64		T1	3158		T11	4721
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5407318	1			T22	19		T1	4644		T11	8937
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3897832	1			T22	154		T1	9276		T11	15169
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1440392	1			T22	94		T1	3368		T11	4591
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1873983	1			T22	29		T1	281		T11	480
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	409664	1			T22	267		T1	4724		T11	6879
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1432828	1			T22	104		T1	3340		T11	4475
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5414121	1			T22	22		T1	4620		T11	9093
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3897110	1			T22	187		T1	9148		T11	15455
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1447126	1			T22	80		T1	3484		T11	4532
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1869349	1			T22	31		T1	251		T11	437
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	405119	1			T22	272		T1	4822		T11	6292
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1429192	1			T22	75		T1	3308		T11	4722
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5407073	1			T22	36		T1	4692		T11	8991
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3896246	1			T22	252		T1	9552		T11	15489
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1441775	1			T22	112		T1	3569		T11	4415
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1874140	1			T22	21		T1	258		T11	476
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	409432	1			T22	150		T1	4445		T11	6632
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1433351	1			T22	96		T1	3117		T11	4528
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5388897	1			T22	25		T1	4680		T11	8997
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3904878	1			T22	254		T1	9494		T11	15346
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1441822	1			T22	59		T1	3361		T11	4378
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1882980	1			T22	26		T1	271		T11	528
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	407726	1			T22	210		T1	4480		T11	6885
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1435714	1			T22	93		T1	3347		T11	4397
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5410973	1			T22	22		T1	4664		T11	8889
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3896685	1			T22	227		T1	9200		T11	15629
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1445158	1			T22	97		T1	3412		T11	4731
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1871567	1			T22	19		T1	302		T11	462
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	408427	1			T22	212		T1	4718		T11	6486
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1429207	1			T22	90		T1	3337		T11	4334
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5407707	1			T22	28		T1	4683		T11	9067
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3894708	1			T22	247		T1	8920		T11	15950
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1442585	1			T22	85		T1	3276		T11	4587
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1874786	1			T22	15		T1	273		T11	356
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	409081	1			T22	190		T1	5028		T11	6141
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1433150	1			T22	102		T1	3453		T11	4430
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5407727	1			T22	16		T1	4636		T11	8944
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3897716	1			T22	133		T1	9099		T11	14964
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1446531	1			T22	50		T1	3405		T11	4760
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1872908	1			T22	37		T1	294		T11	573
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	409500	1			T22	297		T1	4752		T11	6701
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1427635	1			T22	134		T1	3447		T11	4589
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5407295	1			T22	10		T1	4723		T11	9053
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3896106	1			T22	198		T1	9048		T11	15495
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1444757	1			T22	48		T1	3561		T11	4805
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1872258	1			T22	32		T1	296		T11	449
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	406329	1			T22	268		T1	4601		T11	6443
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1435272	1			T22	111		T1	3404		T11	4286
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5388069	1			T22	21		T1	4580		T11	8933
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3911484	1			T22	166		T1	9100		T11	15701
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1446674	1			T22	80		T1	3486		T11	4458
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1875287	1			T22	35		T1	294		T11	535
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	407215	1			T22	259		T1	4677		T11	6443
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1433288	1			T22	106		T1	3496		T11	4461
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5406046	1			T22	34		T1	4601		T11	9085
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3895621	1			T22	291		T1	9276		T11	15860
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1441424	1			T22	85		T1	3397		T11	4545
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1872780	1			T22	17		T1	297		T11	412
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	412377	1			T22	188		T1	4776		T11	6180
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1433769	1			T22	52		T1	3286		T11	4449
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5412592	1			T22	23		T1	4644		T11	8938
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3891645	1			T22	237		T1	9209		T11	15443
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1440244	1			T22	119		T1	3387		T11	4246
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1874302	1			T22	19		T1	288		T11	460
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	409044	1			T22	179		T1	4643		T11	6756
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1434190	1			T22	90		T1	3462		T11	4688
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5411120	1			T22	8		T1	4624		T11	8821
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3898203	1			T22	169		T1	9025		T11	15317
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1443547	1			T22	79		T1	3583		T11	4331
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1873393	1			T22	40		T1	237		T11	488
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	405361	1			T22	257		T1	4522		T11	7013
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1430393	1			T22	114		T1	3642		T11	4561
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5419368	1			T22	34		T1	4700		T11	8815
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3895096	1			T22	259		T1	9522		T11	15501
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1434993	1			T22	72		T1	3332		T11	4849
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1874941	1			T22	18		T1	249		T11	479
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	411115	1			T22	202		T1	4749		T11	6261
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1426504	1			T22	82		T1	3081		T11	4626
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5410981	1			T22	21		T1	4717		T11	8884
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3895844	1			T22	195		T1	9052		T11	15176
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1442108	1			T22	31		T1	3928		T11	4695
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1878459	1			T22	27		T1	300		T11	537
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	408373	1			T22	296		T1	4483		T11	6505
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1426252	1			T22	97		T1	3153		T11	4734
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5422801	1			T22	39		T1	4580		T11	9037
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3889858	1			T22	294		T1	9265		T11	15597
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1437784	1			T22	88		T1	3269		T11	4466
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1877239	1			T22	25		T1	323		T11	472
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	408576	1			T22	184		T1	4848		T11	6703
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1425759	1			T22	37		T1	3348		T11	4256
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5408258	1			T22	24		T1	4734		T11	8948
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3900915	1			T22	242		T1	9244		T11	15294
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1442924	1			T22	73		T1	3474		T11	4657
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1871566	1			T22	28		T1	241		T11	423
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	408546	1			T22	246		T1	4775		T11	6579
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1429808	1			T22	54		T1	3165		T11	4630
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5429765	1			T22	17		T1	4638		T11	8986
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3885086	1			T22	267		T1	9166		T11	15595
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1439574	1			T22	116		T1	3305		T11	4548
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1875402	1			T22	27		T1	280		T11	429
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	410299	1			T22	159		T1	4716		T11	6517
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1421891	1			T22	81		T1	3528		T11	4456
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5412685	1			T22	32		T1	4630		T11	8872
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3892614	1			T22	224		T1	9319		T11	15228
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1440873	1			T22	107		T1	3338		T11	4672
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1875096	1			T22	19		T1	227		T11	550
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	411282	1			T22	202		T1	4692		T11	6752
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1429467	1			T22	83		T1	3427		T11	4457
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5412485	1			T22	20		T1	4756		T11	9052
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3898112	1			T22	170		T1	9011		T11	15420
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1439315	1			T22	67		T1	3357		T11	4747
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1875641	1			T22	29		T1	304		T11	393
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	409175	1			T22	279		T1	4860		T11	6580
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1427289	1			T22	102		T1	3345		T11	4339
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5424865	1			T22	17		T1	4652		T11	8919
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3887423	1			T22	230		T1	9090		T11	15743
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1435466	1			T22	76		T1	3302		T11	4613
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1875861	1			T22	26		T1	294		T11	433
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	409627	1			T22	231		T1	4852		T11	6297
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1428775	1			T22	87		T1	3443		T11	4526
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5420743	1			T22	14		T1	4654		T11	8833
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3885993	1			T22	174		T1	9413		T11	15538
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1433911	1			T22	65		T1	3514		T11	4604
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1878184	1			T22	44		T1	276		T11	544
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	408947	1			T22	222		T1	4517		T11	6525
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1434239	1			T22	148		T1	3259		T11	4487
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5416960	1			T22	34		T1	4640		T11	8929
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3897217	1			T22	256		T1	9313		T11	15526
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1441708	1			T22	84		T1	3279		T11	4541
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1872667	1			T22	13		T1	309		T11	454
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	409060	1			T22	214		T1	4873		T11	6591
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1424405	1			T22	66		T1	3219		T11	4490
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5416689	1			T22	23		T1	4706		T11	8911
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3898750	1			T22	293		T1	9059		T11	15843
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1444583	1			T22	52		T1	3584		T11	4600
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1870585	1			T22	24		T1	305		T11	418
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	406499	1			T22	215		T1	4597		T11	6426
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1424911	1			T22	60		T1	3382		T11	4333
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5408048	1			T22	22		T1	4752		T11	8987
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3901586	1			T22	248		T1	9326		T11	15543
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1443349	1			T22	72		T1	3403		T11	4511
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1875772	1			T22	24		T1	249		T11	491
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	408588	1			T22	251		T1	4614		T11	6543
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1424674	1			T22	50		T1	3289		T11	4456
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5406362	1			T22	32		T1	4639		T11	8881
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3897834	1			T22	290		T1	9212		T11	15419
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1436817	1			T22	104		T1	3461		T11	4457
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1879204	1			T22	13		T1	282		T11	525
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	411408	1			T22	166		T1	4723		T11	6700
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1430392	1			T22	62		T1	3316		T11	4549
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5399842	1			T22	21		T1	4689		T11	9143
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3907710	1			T22	206		T1	9333		T11	15689
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1437840	1			T22	85		T1	3492		T11	4508
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1877412	1			T22	35		T1	236		T11	413
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	410783	1			T22	257		T1	4469		T11	6338
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1428430	1			T22	63		T1	3414		T11	4440
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5412488	1			T22	26		T1	4609		T11	8844
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3903045	1			T22	241		T1	9319		T11	15321
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1432587	1			T22	139		T1	3530		T11	4660
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1878935	1			T22	23		T1	253		T11	569
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	411107	1			T22	185		T1	4647		T11	6531
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1423855	1			T22	53		T1	3275		T11	4606
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5412693	1			T22	31		T1	4686		T11	8892
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3904877	1			T22	263		T1	9320		T11	15768
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1441005	1			T22	87		T1	3569		T11	4682
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1870842	1			T22	24		T1	277		T11	398
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	407727	1			T22	176		T1	4602		T11	6329
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1424873	1			T22	86		T1	3179		T11	4462

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal