Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[1]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[2]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[3]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[4]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[5]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[6]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[7]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[8]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[9]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[10]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[11]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[12]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[13]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[14]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[15]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[16]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[17]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[18]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[19]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[20]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[21]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[22]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[23]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[24]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[25]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[26]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[27]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[28]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[29]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[30]	14462017	1			T22	667		T1	25633		T11	40531
bins_for_gpio_bits[31]	14462017	1			T22	667		T1	25633		T11	40531

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

279243073

1

T22

4270

T1

268014

T11

448080

auto[1]

183541471

1

T22

17074

T1

552242

T11

848912

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

279235235

1

T22

4277

T1

268065

T11

448145

auto[1]

183549309

1

T22

17067

T1

552191

T11

848847

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	8464276	1			T22	142		T1	7664		T11	13235
bins_for_gpio_bits[0]	auto[0]	auto[1]	255961	1			T22	21		T1	592		T11	811
bins_for_gpio_bits[0]	auto[1]	auto[0]	256213	1			T22	21		T1	589		T11	807
bins_for_gpio_bits[0]	auto[1]	auto[1]	5485567	1			T22	483		T1	16788		T11	25678
bins_for_gpio_bits[1]	auto[0]	auto[0]	8470816	1			T22	112		T1	7759		T11	13507
bins_for_gpio_bits[1]	auto[0]	auto[1]	256042	1			T22	16		T1	557		T11	795
bins_for_gpio_bits[1]	auto[1]	auto[0]	256284	1			T22	16		T1	556		T11	793
bins_for_gpio_bits[1]	auto[1]	auto[1]	5478875	1			T22	523		T1	16761		T11	25436
bins_for_gpio_bits[2]	auto[0]	auto[0]	8469409	1			T22	150		T1	7947		T11	13196
bins_for_gpio_bits[2]	auto[0]	auto[1]	256001	1			T22	19		T1	567		T11	784
bins_for_gpio_bits[2]	auto[1]	auto[0]	256231	1			T22	19		T1	564		T11	782
bins_for_gpio_bits[2]	auto[1]	auto[1]	5480376	1			T22	479		T1	16555		T11	25769
bins_for_gpio_bits[3]	auto[0]	auto[0]	8467693	1			T22	101		T1	7661		T11	12948
bins_for_gpio_bits[3]	auto[0]	auto[1]	255503	1			T22	12		T1	530		T11	760
bins_for_gpio_bits[3]	auto[1]	auto[0]	255769	1			T22	12		T1	528		T11	758
bins_for_gpio_bits[3]	auto[1]	auto[1]	5483052	1			T22	542		T1	16914		T11	26065
bins_for_gpio_bits[4]	auto[0]	auto[0]	8464984	1			T22	127		T1	7729		T11	13223
bins_for_gpio_bits[4]	auto[0]	auto[1]	256461	1			T22	15		T1	565		T11	787
bins_for_gpio_bits[4]	auto[1]	auto[0]	256709	1			T22	15		T1	564		T11	785
bins_for_gpio_bits[4]	auto[1]	auto[1]	5483863	1			T22	510		T1	16775		T11	25736
bins_for_gpio_bits[5]	auto[0]	auto[0]	8474200	1			T22	121		T1	7780		T11	13228
bins_for_gpio_bits[5]	auto[0]	auto[1]	256159	1			T22	13		T1	575		T11	835
bins_for_gpio_bits[5]	auto[1]	auto[0]	256396	1			T22	12		T1	575		T11	834
bins_for_gpio_bits[5]	auto[1]	auto[1]	5475262	1			T22	521		T1	16703		T11	25634
bins_for_gpio_bits[6]	auto[0]	auto[0]	8465931	1			T22	152		T1	7920		T11	13092
bins_for_gpio_bits[6]	auto[0]	auto[1]	256815	1			T22	17		T1	602		T11	792
bins_for_gpio_bits[6]	auto[1]	auto[0]	257057	1			T22	17		T1	599		T11	790
bins_for_gpio_bits[6]	auto[1]	auto[1]	5482214	1			T22	481		T1	16512		T11	25857
bins_for_gpio_bits[7]	auto[0]	auto[0]	8456432	1			T22	98		T1	7743		T11	13141
bins_for_gpio_bits[7]	auto[0]	auto[1]	257011	1			T22	12		T1	571		T11	762
bins_for_gpio_bits[7]	auto[1]	auto[0]	257267	1			T22	12		T1	569		T11	762
bins_for_gpio_bits[7]	auto[1]	auto[1]	5491307	1			T22	545		T1	16750		T11	25866
bins_for_gpio_bits[8]	auto[0]	auto[0]	8471052	1			T22	120		T1	7794		T11	13266
bins_for_gpio_bits[8]	auto[0]	auto[1]	256355	1			T22	18		T1	584		T11	817
bins_for_gpio_bits[8]	auto[1]	auto[0]	256646	1			T22	18		T1	584		T11	816
bins_for_gpio_bits[8]	auto[1]	auto[1]	5477964	1			T22	511		T1	16671		T11	25632
bins_for_gpio_bits[9]	auto[0]	auto[0]	8468197	1			T22	111		T1	7687		T11	13174
bins_for_gpio_bits[9]	auto[0]	auto[1]	256622	1			T22	17		T1	545		T11	838
bins_for_gpio_bits[9]	auto[1]	auto[0]	256881	1			T22	17		T1	545		T11	836
bins_for_gpio_bits[9]	auto[1]	auto[1]	5480317	1			T22	522		T1	16856		T11	25683
bins_for_gpio_bits[10]	auto[0]	auto[0]	8470552	1			T22	94		T1	7788		T11	13470
bins_for_gpio_bits[10]	auto[0]	auto[1]	256367	1			T22	10		T1	549		T11	807
bins_for_gpio_bits[10]	auto[1]	auto[0]	256614	1			T22	9		T1	547		T11	807
bins_for_gpio_bits[10]	auto[1]	auto[1]	5478484	1			T22	554		T1	16749		T11	25447
bins_for_gpio_bits[11]	auto[0]	auto[0]	8467872	1			T22	78		T1	7998		T11	13492
bins_for_gpio_bits[11]	auto[0]	auto[1]	256208	1			T22	12		T1	586		T11	816
bins_for_gpio_bits[11]	auto[1]	auto[0]	256438	1			T22	12		T1	582		T11	815
bins_for_gpio_bits[11]	auto[1]	auto[1]	5481499	1			T22	565		T1	16467		T11	25408
bins_for_gpio_bits[12]	auto[0]	auto[0]	8453762	1			T22	122		T1	7791		T11	13141
bins_for_gpio_bits[12]	auto[0]	auto[1]	255982	1			T22	14		T1	571		T11	786
bins_for_gpio_bits[12]	auto[1]	auto[0]	256268	1			T22	14		T1	569		T11	785
bins_for_gpio_bits[12]	auto[1]	auto[1]	5496005	1			T22	517		T1	16702		T11	25819
bins_for_gpio_bits[13]	auto[0]	auto[0]	8464238	1			T22	122		T1	7742		T11	13232
bins_for_gpio_bits[13]	auto[0]	auto[1]	255816	1			T22	15		T1	556		T11	812
bins_for_gpio_bits[13]	auto[1]	auto[0]	256012	1			T22	14		T1	553		T11	810
bins_for_gpio_bits[13]	auto[1]	auto[1]	5485951	1			T22	516		T1	16782		T11	25677
bins_for_gpio_bits[14]	auto[0]	auto[0]	8470401	1			T22	143		T1	7768		T11	12861
bins_for_gpio_bits[14]	auto[0]	auto[1]	256481	1			T22	18		T1	553		T11	784
bins_for_gpio_bits[14]	auto[1]	auto[0]	256737	1			T22	18		T1	551		T11	783
bins_for_gpio_bits[14]	auto[1]	auto[1]	5478398	1			T22	488		T1	16761		T11	26103
bins_for_gpio_bits[15]	auto[0]	auto[0]	8471880	1			T22	111		T1	7867		T11	12841
bins_for_gpio_bits[15]	auto[0]	auto[1]	255937	1			T22	17		T1	578		T11	801
bins_for_gpio_bits[15]	auto[1]	auto[0]	256180	1			T22	16		T1	577		T11	799
bins_for_gpio_bits[15]	auto[1]	auto[1]	5478020	1			T22	523		T1	16611		T11	26090
bins_for_gpio_bits[16]	auto[0]	auto[0]	8473246	1			T22	107		T1	7731		T11	13305
bins_for_gpio_bits[16]	auto[0]	auto[1]	255811	1			T22	17		T1	551		T11	840
bins_for_gpio_bits[16]	auto[1]	auto[0]	256056	1			T22	17		T1	550		T11	838
bins_for_gpio_bits[16]	auto[1]	auto[1]	5476904	1			T22	526		T1	16801		T11	25548
bins_for_gpio_bits[17]	auto[0]	auto[0]	8474847	1			T22	72		T1	8361		T11	13282
bins_for_gpio_bits[17]	auto[0]	auto[1]	256470	1			T22	7		T1	584		T11	840
bins_for_gpio_bits[17]	auto[1]	auto[0]	256701	1			T22	7		T1	584		T11	834
bins_for_gpio_bits[17]	auto[1]	auto[1]	5473999	1			T22	581		T1	16104		T11	25575
bins_for_gpio_bits[18]	auto[0]	auto[0]	8481547	1			T22	135		T1	7630		T11	13189
bins_for_gpio_bits[18]	auto[0]	auto[1]	256062	1			T22	17		T1	544		T11	788
bins_for_gpio_bits[18]	auto[1]	auto[0]	256277	1			T22	17		T1	542		T11	786
bins_for_gpio_bits[18]	auto[1]	auto[1]	5468131	1			T22	498		T1	16917		T11	25768
bins_for_gpio_bits[19]	auto[0]	auto[0]	8466176	1			T22	111		T1	7882		T11	13247
bins_for_gpio_bits[19]	auto[0]	auto[1]	256359	1			T22	14		T1	568		T11	784
bins_for_gpio_bits[19]	auto[1]	auto[0]	256572	1			T22	14		T1	567		T11	781
bins_for_gpio_bits[19]	auto[1]	auto[1]	5482910	1			T22	528		T1	16616		T11	25719
bins_for_gpio_bits[20]	auto[0]	auto[0]	8488949	1			T22	142		T1	7654		T11	13156
bins_for_gpio_bits[20]	auto[0]	auto[1]	255570	1			T22	18		T1	570		T11	808
bins_for_gpio_bits[20]	auto[1]	auto[0]	255792	1			T22	18		T1	569		T11	807
bins_for_gpio_bits[20]	auto[1]	auto[1]	5461706	1			T22	489		T1	16840		T11	25760
bins_for_gpio_bits[21]	auto[0]	auto[0]	8472354	1			T22	139		T1	7643		T11	13280
bins_for_gpio_bits[21]	auto[0]	auto[1]	256015	1			T22	19		T1	553		T11	819
bins_for_gpio_bits[21]	auto[1]	auto[0]	256300	1			T22	19		T1	552		T11	814
bins_for_gpio_bits[21]	auto[1]	auto[1]	5477348	1			T22	490		T1	16885		T11	25618
bins_for_gpio_bits[22]	auto[0]	auto[0]	8471198	1			T22	104		T1	7889		T11	13374
bins_for_gpio_bits[22]	auto[0]	auto[1]	255993	1			T22	12		T1	528		T11	818
bins_for_gpio_bits[22]	auto[1]	auto[0]	256243	1			T22	12		T1	528		T11	818
bins_for_gpio_bits[22]	auto[1]	auto[1]	5478583	1			T22	539		T1	16688		T11	25521
bins_for_gpio_bits[23]	auto[0]	auto[0]	8479825	1			T22	100		T1	7726		T11	13170
bins_for_gpio_bits[23]	auto[0]	auto[1]	256119	1			T22	19		T1	523		T11	797
bins_for_gpio_bits[23]	auto[1]	auto[0]	256367	1			T22	19		T1	522		T11	795
bins_for_gpio_bits[23]	auto[1]	auto[1]	5469706	1			T22	529		T1	16862		T11	25769
bins_for_gpio_bits[24]	auto[0]	auto[0]	8476571	1			T22	111		T1	7891		T11	13160
bins_for_gpio_bits[24]	auto[0]	auto[1]	256063	1			T22	13		T1	556		T11	822
bins_for_gpio_bits[24]	auto[1]	auto[0]	256267	1			T22	12		T1	553		T11	821
bins_for_gpio_bits[24]	auto[1]	auto[1]	5473116	1			T22	531		T1	16633		T11	25728
bins_for_gpio_bits[25]	auto[0]	auto[0]	8475004	1			T22	116		T1	7674		T11	13146
bins_for_gpio_bits[25]	auto[0]	auto[1]	256126	1			T22	15		T1	555		T11	781
bins_for_gpio_bits[25]	auto[1]	auto[0]	256331	1			T22	15		T1	554		T11	778
bins_for_gpio_bits[25]	auto[1]	auto[1]	5474556	1			T22	521		T1	16850		T11	25826
bins_for_gpio_bits[26]	auto[0]	auto[0]	8475279	1			T22	92		T1	8018		T11	13131
bins_for_gpio_bits[26]	auto[0]	auto[1]	256334	1			T22	8		T1	580		T11	798
bins_for_gpio_bits[26]	auto[1]	auto[0]	256578	1			T22	7		T1	577		T11	798
bins_for_gpio_bits[26]	auto[1]	auto[1]	5473826	1			T22	560		T1	16458		T11	25804
bins_for_gpio_bits[27]	auto[0]	auto[0]	8471040	1			T22	106		T1	7847		T11	13202
bins_for_gpio_bits[27]	auto[0]	auto[1]	255863	1			T22	12		T1	559		T11	792
bins_for_gpio_bits[27]	auto[1]	auto[0]	256129	1			T22	12		T1	557		T11	787
bins_for_gpio_bits[27]	auto[1]	auto[1]	5478985	1			T22	537		T1	16670		T11	25750
bins_for_gpio_bits[28]	auto[0]	auto[0]	8465762	1			T22	126		T1	7806		T11	13078
bins_for_gpio_bits[28]	auto[0]	auto[1]	256352	1			T22	23		T1	577		T11	787
bins_for_gpio_bits[28]	auto[1]	auto[0]	256621	1			T22	23		T1	576		T11	785
bins_for_gpio_bits[28]	auto[1]	auto[1]	5483282	1			T22	495		T1	16674		T11	25881
bins_for_gpio_bits[29]	auto[0]	auto[0]	8457867	1			T22	130		T1	7834		T11	13246
bins_for_gpio_bits[29]	auto[0]	auto[1]	256966	1			T22	12		T1	584		T11	821
bins_for_gpio_bits[29]	auto[1]	auto[0]	257227	1			T22	11		T1	583		T11	818
bins_for_gpio_bits[29]	auto[1]	auto[1]	5489957	1			T22	514		T1	16632		T11	25646
bins_for_gpio_bits[30]	auto[0]	auto[0]	8468026	1			T22	166		T1	7833		T11	13249
bins_for_gpio_bits[30]	auto[0]	auto[1]	255768	1			T22	22		T1	562		T11	827
bins_for_gpio_bits[30]	auto[1]	auto[0]	255984	1			T22	22		T1	559		T11	824
bins_for_gpio_bits[30]	auto[1]	auto[1]	5482239	1			T22	457		T1	16679		T11	25631
bins_for_gpio_bits[31]	auto[0]	auto[0]	8467971	1			T22	127		T1	7955		T11	13166
bins_for_gpio_bits[31]	auto[0]	auto[1]	256286	1			T22	15		T1	578		T11	808
bins_for_gpio_bits[31]	auto[1]	auto[0]	256569	1			T22	15		T1	577		T11	806
bins_for_gpio_bits[31]	auto[1]	auto[1]	5481191	1			T22	510		T1	16523		T11	25751