Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8404405 |
1 |
|
|
T22 |
338 |
|
T1 |
14881 |
|
T11 |
21656 |
| auto[1] |
6305090 |
1 |
|
|
T1 |
11484 |
|
T11 |
19938 |
|
T13 |
162 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13900550 |
1 |
|
|
T22 |
338 |
|
T1 |
24994 |
|
T11 |
39283 |
| auto[1] |
808945 |
1 |
|
|
T1 |
1371 |
|
T11 |
2311 |
|
T13 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8409044 |
1 |
|
|
T22 |
338 |
|
T1 |
14016 |
|
T11 |
23213 |
| auto[1] |
6300451 |
1 |
|
|
T1 |
12349 |
|
T11 |
18381 |
|
T13 |
114 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2745833 |
1 |
|
|
T1 |
5555 |
|
T11 |
7729 |
|
T13 |
55 |
| auto[1] |
auto[0] |
auto[1] |
404428 |
1 |
|
|
T1 |
671 |
|
T11 |
1098 |
|
T13 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2745673 |
1 |
|
|
T1 |
5423 |
|
T11 |
8341 |
|
T13 |
49 |
| auto[1] |
auto[1] |
auto[1] |
404517 |
1 |
|
|
T1 |
700 |
|
T11 |
1213 |
|
T13 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8406028 |
1 |
|
|
T22 |
338 |
|
T1 |
14110 |
|
T11 |
21815 |
| auto[1] |
6303467 |
1 |
|
|
T1 |
12255 |
|
T11 |
19779 |
|
T13 |
111 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13904620 |
1 |
|
|
T22 |
338 |
|
T1 |
25171 |
|
T11 |
39160 |
| auto[1] |
804875 |
1 |
|
|
T1 |
1194 |
|
T11 |
2434 |
|
T13 |
13 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8440858 |
1 |
|
|
T22 |
338 |
|
T1 |
15114 |
|
T11 |
22184 |
| auto[1] |
6268637 |
1 |
|
|
T1 |
11251 |
|
T11 |
19410 |
|
T13 |
145 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2733372 |
1 |
|
|
T1 |
4950 |
|
T11 |
7916 |
|
T13 |
72 |
| auto[1] |
auto[0] |
auto[1] |
400907 |
1 |
|
|
T1 |
572 |
|
T11 |
1116 |
|
T13 |
10 |
| auto[1] |
auto[1] |
auto[0] |
2730390 |
1 |
|
|
T1 |
5107 |
|
T11 |
9060 |
|
T13 |
60 |
| auto[1] |
auto[1] |
auto[1] |
403968 |
1 |
|
|
T1 |
622 |
|
T11 |
1318 |
|
T13 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8388299 |
1 |
|
|
T22 |
338 |
|
T1 |
14945 |
|
T11 |
21977 |
| auto[1] |
6321196 |
1 |
|
|
T1 |
11420 |
|
T11 |
19617 |
|
T13 |
182 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13898805 |
1 |
|
|
T22 |
338 |
|
T1 |
25108 |
|
T11 |
39020 |
| auto[1] |
810690 |
1 |
|
|
T1 |
1257 |
|
T11 |
2574 |
|
T13 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8405163 |
1 |
|
|
T22 |
338 |
|
T1 |
14659 |
|
T11 |
21556 |
| auto[1] |
6304332 |
1 |
|
|
T1 |
11706 |
|
T11 |
20038 |
|
T13 |
140 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2741943 |
1 |
|
|
T1 |
5480 |
|
T11 |
8446 |
|
T13 |
50 |
| auto[1] |
auto[0] |
auto[1] |
404126 |
1 |
|
|
T1 |
686 |
|
T11 |
1245 |
|
T13 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2751699 |
1 |
|
|
T1 |
4969 |
|
T11 |
9018 |
|
T13 |
82 |
| auto[1] |
auto[1] |
auto[1] |
406564 |
1 |
|
|
T1 |
571 |
|
T11 |
1329 |
|
T13 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8422135 |
1 |
|
|
T22 |
338 |
|
T1 |
15410 |
|
T11 |
22380 |
| auto[1] |
6287360 |
1 |
|
|
T1 |
10955 |
|
T11 |
19214 |
|
T13 |
159 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13896617 |
1 |
|
|
T22 |
338 |
|
T1 |
25138 |
|
T11 |
39392 |
| auto[1] |
812878 |
1 |
|
|
T1 |
1227 |
|
T11 |
2202 |
|
T13 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8401749 |
1 |
|
|
T22 |
338 |
|
T1 |
15565 |
|
T11 |
24277 |
| auto[1] |
6307746 |
1 |
|
|
T1 |
10800 |
|
T11 |
17317 |
|
T13 |
118 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2756340 |
1 |
|
|
T1 |
5120 |
|
T11 |
7369 |
|
T13 |
21 |
| auto[1] |
auto[0] |
auto[1] |
407515 |
1 |
|
|
T1 |
656 |
|
T11 |
1046 |
|
T13 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2738528 |
1 |
|
|
T1 |
4453 |
|
T11 |
7746 |
|
T13 |
91 |
| auto[1] |
auto[1] |
auto[1] |
405363 |
1 |
|
|
T1 |
571 |
|
T11 |
1156 |
|
T13 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8396964 |
1 |
|
|
T22 |
338 |
|
T1 |
14671 |
|
T11 |
24612 |
| auto[1] |
6312531 |
1 |
|
|
T1 |
11694 |
|
T11 |
16982 |
|
T13 |
166 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13903062 |
1 |
|
|
T22 |
338 |
|
T1 |
25322 |
|
T11 |
39139 |
| auto[1] |
806433 |
1 |
|
|
T1 |
1043 |
|
T11 |
2455 |
|
T13 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8434165 |
1 |
|
|
T22 |
338 |
|
T1 |
15364 |
|
T11 |
22493 |
| auto[1] |
6275330 |
1 |
|
|
T1 |
11001 |
|
T11 |
19101 |
|
T13 |
136 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2720961 |
1 |
|
|
T1 |
4785 |
|
T11 |
8927 |
|
T13 |
33 |
| auto[1] |
auto[0] |
auto[1] |
400559 |
1 |
|
|
T1 |
481 |
|
T11 |
1352 |
|
T13 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2747936 |
1 |
|
|
T1 |
5173 |
|
T11 |
7719 |
|
T13 |
96 |
| auto[1] |
auto[1] |
auto[1] |
405874 |
1 |
|
|
T1 |
562 |
|
T11 |
1103 |
|
T13 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8392401 |
1 |
|
|
T22 |
338 |
|
T1 |
15086 |
|
T11 |
22554 |
| auto[1] |
6317094 |
1 |
|
|
T1 |
11279 |
|
T11 |
19040 |
|
T13 |
141 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13898892 |
1 |
|
|
T22 |
338 |
|
T1 |
25049 |
|
T11 |
39326 |
| auto[1] |
810603 |
1 |
|
|
T1 |
1316 |
|
T11 |
2268 |
|
T13 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8408327 |
1 |
|
|
T22 |
338 |
|
T1 |
14559 |
|
T11 |
23225 |
| auto[1] |
6301168 |
1 |
|
|
T1 |
11806 |
|
T11 |
18369 |
|
T13 |
139 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2740078 |
1 |
|
|
T1 |
5637 |
|
T11 |
7608 |
|
T13 |
64 |
| auto[1] |
auto[0] |
auto[1] |
404946 |
1 |
|
|
T1 |
784 |
|
T11 |
1090 |
|
T13 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2750487 |
1 |
|
|
T1 |
4853 |
|
T11 |
8493 |
|
T13 |
66 |
| auto[1] |
auto[1] |
auto[1] |
405657 |
1 |
|
|
T1 |
532 |
|
T11 |
1178 |
|
T13 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8386347 |
1 |
|
|
T22 |
338 |
|
T1 |
14926 |
|
T11 |
21742 |
| auto[1] |
6323148 |
1 |
|
|
T1 |
11439 |
|
T11 |
19852 |
|
T13 |
105 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13905401 |
1 |
|
|
T22 |
338 |
|
T1 |
24998 |
|
T11 |
39065 |
| auto[1] |
804094 |
1 |
|
|
T1 |
1367 |
|
T11 |
2529 |
|
T13 |
14 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8437197 |
1 |
|
|
T22 |
338 |
|
T1 |
14219 |
|
T11 |
22074 |
| auto[1] |
6272298 |
1 |
|
|
T1 |
12146 |
|
T11 |
19520 |
|
T13 |
159 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2729693 |
1 |
|
|
T1 |
5527 |
|
T11 |
7697 |
|
T13 |
83 |
| auto[1] |
auto[0] |
auto[1] |
399889 |
1 |
|
|
T1 |
669 |
|
T11 |
1064 |
|
T13 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2738511 |
1 |
|
|
T1 |
5252 |
|
T11 |
9294 |
|
T13 |
62 |
| auto[1] |
auto[1] |
auto[1] |
404205 |
1 |
|
|
T1 |
698 |
|
T11 |
1465 |
|
T13 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8396175 |
1 |
|
|
T22 |
338 |
|
T1 |
13699 |
|
T11 |
24090 |
| auto[1] |
6313320 |
1 |
|
|
T1 |
12666 |
|
T11 |
17504 |
|
T13 |
118 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13902133 |
1 |
|
|
T22 |
338 |
|
T1 |
25192 |
|
T11 |
39321 |
| auto[1] |
807362 |
1 |
|
|
T1 |
1173 |
|
T11 |
2273 |
|
T13 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8413901 |
1 |
|
|
T22 |
338 |
|
T1 |
15255 |
|
T11 |
23170 |
| auto[1] |
6295594 |
1 |
|
|
T1 |
11110 |
|
T11 |
18424 |
|
T13 |
127 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2747947 |
1 |
|
|
T1 |
4515 |
|
T11 |
8423 |
|
T13 |
68 |
| auto[1] |
auto[0] |
auto[1] |
403404 |
1 |
|
|
T1 |
531 |
|
T11 |
1152 |
|
T13 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2740285 |
1 |
|
|
T1 |
5422 |
|
T11 |
7728 |
|
T13 |
52 |
| auto[1] |
auto[1] |
auto[1] |
403958 |
1 |
|
|
T1 |
642 |
|
T11 |
1121 |
|
T13 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8420779 |
1 |
|
|
T22 |
338 |
|
T1 |
14272 |
|
T11 |
22032 |
| auto[1] |
6288716 |
1 |
|
|
T1 |
12093 |
|
T11 |
19562 |
|
T13 |
82 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13902720 |
1 |
|
|
T22 |
338 |
|
T1 |
25134 |
|
T11 |
38872 |
| auto[1] |
806775 |
1 |
|
|
T1 |
1231 |
|
T11 |
2722 |
|
T13 |
14 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8425587 |
1 |
|
|
T22 |
338 |
|
T1 |
14463 |
|
T11 |
21147 |
| auto[1] |
6283908 |
1 |
|
|
T1 |
11902 |
|
T11 |
20447 |
|
T13 |
205 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2723474 |
1 |
|
|
T1 |
4901 |
|
T11 |
7930 |
|
T13 |
126 |
| auto[1] |
auto[0] |
auto[1] |
399484 |
1 |
|
|
T1 |
474 |
|
T11 |
1163 |
|
T13 |
9 |
| auto[1] |
auto[1] |
auto[0] |
2753659 |
1 |
|
|
T1 |
5770 |
|
T11 |
9795 |
|
T13 |
65 |
| auto[1] |
auto[1] |
auto[1] |
407291 |
1 |
|
|
T1 |
757 |
|
T11 |
1559 |
|
T13 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8414767 |
1 |
|
|
T22 |
338 |
|
T1 |
15105 |
|
T11 |
21755 |
| auto[1] |
6294728 |
1 |
|
|
T1 |
11260 |
|
T11 |
19839 |
|
T13 |
146 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13907013 |
1 |
|
|
T22 |
338 |
|
T1 |
25282 |
|
T11 |
39068 |
| auto[1] |
802482 |
1 |
|
|
T1 |
1083 |
|
T11 |
2526 |
|
T13 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8448082 |
1 |
|
|
T22 |
338 |
|
T1 |
15882 |
|
T11 |
21746 |
| auto[1] |
6261413 |
1 |
|
|
T1 |
10483 |
|
T11 |
19848 |
|
T13 |
126 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2727450 |
1 |
|
|
T1 |
5067 |
|
T11 |
7940 |
|
T13 |
42 |
| auto[1] |
auto[0] |
auto[1] |
400283 |
1 |
|
|
T1 |
557 |
|
T11 |
1155 |
|
T13 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2731481 |
1 |
|
|
T1 |
4333 |
|
T11 |
9382 |
|
T13 |
76 |
| auto[1] |
auto[1] |
auto[1] |
402199 |
1 |
|
|
T1 |
526 |
|
T11 |
1371 |
|
T13 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8432975 |
1 |
|
|
T22 |
338 |
|
T1 |
15545 |
|
T11 |
22396 |
| auto[1] |
6276520 |
1 |
|
|
T1 |
10820 |
|
T11 |
19198 |
|
T13 |
149 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13902700 |
1 |
|
|
T22 |
338 |
|
T1 |
25064 |
|
T11 |
39343 |
| auto[1] |
806795 |
1 |
|
|
T1 |
1301 |
|
T11 |
2251 |
|
T13 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8428108 |
1 |
|
|
T22 |
338 |
|
T1 |
14298 |
|
T11 |
23651 |
| auto[1] |
6281387 |
1 |
|
|
T1 |
12067 |
|
T11 |
17943 |
|
T13 |
121 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2746332 |
1 |
|
|
T1 |
5957 |
|
T11 |
7807 |
|
T13 |
39 |
| auto[1] |
auto[0] |
auto[1] |
404905 |
1 |
|
|
T1 |
713 |
|
T11 |
1097 |
|
T13 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2728260 |
1 |
|
|
T1 |
4809 |
|
T11 |
7885 |
|
T13 |
73 |
| auto[1] |
auto[1] |
auto[1] |
401890 |
1 |
|
|
T1 |
588 |
|
T11 |
1154 |
|
T13 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8436453 |
1 |
|
|
T22 |
338 |
|
T1 |
13768 |
|
T11 |
21466 |
| auto[1] |
6273042 |
1 |
|
|
T1 |
12597 |
|
T11 |
20128 |
|
T13 |
93 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13901451 |
1 |
|
|
T22 |
338 |
|
T1 |
25063 |
|
T11 |
39095 |
| auto[1] |
808044 |
1 |
|
|
T1 |
1302 |
|
T11 |
2499 |
|
T13 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8414590 |
1 |
|
|
T22 |
338 |
|
T1 |
14310 |
|
T11 |
21800 |
| auto[1] |
6294905 |
1 |
|
|
T1 |
12055 |
|
T11 |
19794 |
|
T13 |
130 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2751448 |
1 |
|
|
T1 |
5134 |
|
T11 |
8183 |
|
T13 |
64 |
| auto[1] |
auto[0] |
auto[1] |
405412 |
1 |
|
|
T1 |
604 |
|
T11 |
1168 |
|
T13 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2735413 |
1 |
|
|
T1 |
5619 |
|
T11 |
9112 |
|
T13 |
57 |
| auto[1] |
auto[1] |
auto[1] |
402632 |
1 |
|
|
T1 |
698 |
|
T11 |
1331 |
|
T13 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8428642 |
1 |
|
|
T22 |
338 |
|
T1 |
15352 |
|
T11 |
24605 |
| auto[1] |
6280853 |
1 |
|
|
T1 |
11013 |
|
T11 |
16989 |
|
T13 |
92 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13900698 |
1 |
|
|
T22 |
338 |
|
T1 |
25223 |
|
T11 |
38981 |
| auto[1] |
808797 |
1 |
|
|
T1 |
1142 |
|
T11 |
2613 |
|
T13 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8408341 |
1 |
|
|
T22 |
338 |
|
T1 |
15507 |
|
T11 |
21456 |
| auto[1] |
6301154 |
1 |
|
|
T1 |
10858 |
|
T11 |
20138 |
|
T13 |
166 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2751361 |
1 |
|
|
T1 |
5157 |
|
T11 |
9435 |
|
T13 |
89 |
| auto[1] |
auto[0] |
auto[1] |
405170 |
1 |
|
|
T1 |
647 |
|
T11 |
1459 |
|
T13 |
9 |
| auto[1] |
auto[1] |
auto[0] |
2740996 |
1 |
|
|
T1 |
4559 |
|
T11 |
8090 |
|
T13 |
65 |
| auto[1] |
auto[1] |
auto[1] |
403627 |
1 |
|
|
T1 |
495 |
|
T11 |
1154 |
|
T13 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8411720 |
1 |
|
|
T22 |
338 |
|
T1 |
13937 |
|
T11 |
22995 |
| auto[1] |
6297775 |
1 |
|
|
T1 |
12428 |
|
T11 |
18599 |
|
T13 |
153 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13902397 |
1 |
|
|
T22 |
338 |
|
T1 |
25180 |
|
T11 |
39290 |
| auto[1] |
807098 |
1 |
|
|
T1 |
1185 |
|
T11 |
2304 |
|
T13 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8421258 |
1 |
|
|
T22 |
338 |
|
T1 |
14743 |
|
T11 |
23180 |
| auto[1] |
6288237 |
1 |
|
|
T1 |
11622 |
|
T11 |
18414 |
|
T13 |
133 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2740650 |
1 |
|
|
T1 |
4930 |
|
T11 |
7518 |
|
T13 |
54 |
| auto[1] |
auto[0] |
auto[1] |
403865 |
1 |
|
|
T1 |
541 |
|
T11 |
1091 |
|
T13 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2740489 |
1 |
|
|
T1 |
5507 |
|
T11 |
8592 |
|
T13 |
69 |
| auto[1] |
auto[1] |
auto[1] |
403233 |
1 |
|
|
T1 |
644 |
|
T11 |
1213 |
|
T13 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8399096 |
1 |
|
|
T22 |
338 |
|
T1 |
15282 |
|
T11 |
23176 |
| auto[1] |
6310399 |
1 |
|
|
T1 |
11083 |
|
T11 |
18418 |
|
T13 |
101 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13898567 |
1 |
|
|
T22 |
338 |
|
T1 |
25011 |
|
T11 |
39357 |
| auto[1] |
810928 |
1 |
|
|
T1 |
1354 |
|
T11 |
2237 |
|
T13 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8398083 |
1 |
|
|
T22 |
338 |
|
T1 |
14088 |
|
T11 |
23217 |
| auto[1] |
6311412 |
1 |
|
|
T1 |
12277 |
|
T11 |
18377 |
|
T13 |
77 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2745387 |
1 |
|
|
T1 |
5683 |
|
T11 |
8111 |
|
T13 |
49 |
| auto[1] |
auto[0] |
auto[1] |
405071 |
1 |
|
|
T1 |
691 |
|
T11 |
1087 |
|
T13 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2755097 |
1 |
|
|
T1 |
5240 |
|
T11 |
8029 |
|
T13 |
22 |
| auto[1] |
auto[1] |
auto[1] |
405857 |
1 |
|
|
T1 |
663 |
|
T11 |
1150 |
|
T13 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8440956 |
1 |
|
|
T22 |
338 |
|
T1 |
14220 |
|
T11 |
22747 |
| auto[1] |
6268539 |
1 |
|
|
T1 |
12145 |
|
T11 |
18847 |
|
T13 |
128 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13904049 |
1 |
|
|
T22 |
338 |
|
T1 |
25122 |
|
T11 |
39185 |
| auto[1] |
805446 |
1 |
|
|
T1 |
1243 |
|
T11 |
2409 |
|
T13 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8426951 |
1 |
|
|
T22 |
338 |
|
T1 |
14369 |
|
T11 |
22909 |
| auto[1] |
6282544 |
1 |
|
|
T1 |
11996 |
|
T11 |
18685 |
|
T13 |
132 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2754117 |
1 |
|
|
T1 |
5356 |
|
T11 |
8026 |
|
T13 |
66 |
| auto[1] |
auto[0] |
auto[1] |
405547 |
1 |
|
|
T1 |
588 |
|
T11 |
1187 |
|
T13 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2722981 |
1 |
|
|
T1 |
5397 |
|
T11 |
8250 |
|
T13 |
56 |
| auto[1] |
auto[1] |
auto[1] |
399899 |
1 |
|
|
T1 |
655 |
|
T11 |
1222 |
|
T13 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8428142 |
1 |
|
|
T22 |
338 |
|
T1 |
14358 |
|
T11 |
22839 |
| auto[1] |
6281353 |
1 |
|
|
T1 |
12007 |
|
T11 |
18755 |
|
T13 |
167 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13904991 |
1 |
|
|
T22 |
338 |
|
T1 |
25181 |
|
T11 |
39209 |
| auto[1] |
804504 |
1 |
|
|
T1 |
1184 |
|
T11 |
2385 |
|
T13 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8437532 |
1 |
|
|
T22 |
338 |
|
T1 |
14848 |
|
T11 |
21848 |
| auto[1] |
6271963 |
1 |
|
|
T1 |
11517 |
|
T11 |
19746 |
|
T13 |
83 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2727298 |
1 |
|
|
T1 |
5414 |
|
T11 |
8593 |
|
T13 |
20 |
| auto[1] |
auto[0] |
auto[1] |
400029 |
1 |
|
|
T1 |
624 |
|
T11 |
1158 |
|
T16 |
20 |
| auto[1] |
auto[1] |
auto[0] |
2740161 |
1 |
|
|
T1 |
4919 |
|
T11 |
8768 |
|
T13 |
56 |
| auto[1] |
auto[1] |
auto[1] |
404475 |
1 |
|
|
T1 |
560 |
|
T11 |
1227 |
|
T13 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8429522 |
1 |
|
|
T22 |
338 |
|
T1 |
14640 |
|
T11 |
21568 |
| auto[1] |
6279973 |
1 |
|
|
T1 |
11725 |
|
T11 |
20026 |
|
T13 |
161 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13902789 |
1 |
|
|
T22 |
338 |
|
T1 |
25014 |
|
T11 |
39329 |
| auto[1] |
806706 |
1 |
|
|
T1 |
1351 |
|
T11 |
2265 |
|
T13 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8429033 |
1 |
|
|
T22 |
338 |
|
T1 |
14137 |
|
T11 |
23051 |
| auto[1] |
6280462 |
1 |
|
|
T1 |
12228 |
|
T11 |
18543 |
|
T13 |
127 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2742961 |
1 |
|
|
T1 |
5786 |
|
T11 |
7885 |
|
T13 |
53 |
| auto[1] |
auto[0] |
auto[1] |
403866 |
1 |
|
|
T1 |
694 |
|
T11 |
1130 |
|
T13 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2730795 |
1 |
|
|
T1 |
5091 |
|
T11 |
8393 |
|
T13 |
64 |
| auto[1] |
auto[1] |
auto[1] |
402840 |
1 |
|
|
T1 |
657 |
|
T11 |
1135 |
|
T13 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8389957 |
1 |
|
|
T22 |
338 |
|
T1 |
14922 |
|
T11 |
22830 |
| auto[1] |
6319538 |
1 |
|
|
T1 |
11443 |
|
T11 |
18764 |
|
T13 |
155 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13908775 |
1 |
|
|
T22 |
338 |
|
T1 |
25065 |
|
T11 |
39194 |
| auto[1] |
800720 |
1 |
|
|
T1 |
1300 |
|
T11 |
2400 |
|
T13 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8463936 |
1 |
|
|
T22 |
338 |
|
T1 |
14259 |
|
T11 |
22674 |
| auto[1] |
6245559 |
1 |
|
|
T1 |
12106 |
|
T11 |
18920 |
|
T13 |
96 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2723143 |
1 |
|
|
T1 |
5812 |
|
T11 |
8934 |
|
T13 |
33 |
| auto[1] |
auto[0] |
auto[1] |
400375 |
1 |
|
|
T1 |
729 |
|
T11 |
1293 |
|
T13 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2721696 |
1 |
|
|
T1 |
4994 |
|
T11 |
7586 |
|
T13 |
54 |
| auto[1] |
auto[1] |
auto[1] |
400345 |
1 |
|
|
T1 |
571 |
|
T11 |
1107 |
|
T13 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8384816 |
1 |
|
|
T22 |
338 |
|
T1 |
14096 |
|
T11 |
21182 |
| auto[1] |
6324679 |
1 |
|
|
T1 |
12269 |
|
T11 |
20412 |
|
T13 |
122 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13906210 |
1 |
|
|
T22 |
338 |
|
T1 |
25092 |
|
T11 |
39165 |
| auto[1] |
803285 |
1 |
|
|
T1 |
1273 |
|
T11 |
2429 |
|
T13 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8446208 |
1 |
|
|
T22 |
338 |
|
T1 |
15097 |
|
T11 |
22538 |
| auto[1] |
6263287 |
1 |
|
|
T1 |
11268 |
|
T11 |
19056 |
|
T13 |
156 |